Method, system, and program product for pre-compile processing of hardware design language (HDL) source files
    2.
    发明授权
    Method, system, and program product for pre-compile processing of hardware design language (HDL) source files 失效
    方法,系统和程序产品,用于硬件设计语言(HDL)源文件的预编译处理

    公开(公告)号:US07506287B2

    公开(公告)日:2009-03-17

    申请号:US11521917

    申请日:2006-09-16

    IPC分类号: G06F17/50

    CPC分类号: G06F11/3664 G06F8/447

    摘要: A method includes pre-compilation operations on HDL source code files, creating a “make it” file, on demand processing of the HDL source code in an HDL source browser, and resolving overloaded function and operator calls in an HDL source code browser debugger. Construct a list of all HDL files a list of HDL files to be processed. Send an HDL file in the list for compiling. If compilation is successful, branch to add the HDL file to an end of target file and that HDL file is removed from the list. The list is tested for remaining files and then a next file in the list is sent for compiling. After all files in the list have been processed, the HDL files which have been processed are checked for failures to compile and if any of said HDL files to be processed have failed to compile the method branches back to repeating the process until all runs are successful.

    摘要翻译: 一种方法包括对HDL源代码文件进行预编译操作,在HDL源浏览器中创建“make it”文件,按需处理HDL源代码,并在HDL源代码浏览器调试器中解析重载函数和操作符调用。 构建所有HDL文件的列表,列出要处理的HDL文件。 在列表中发送一个HDL文件进行编译。 如果编译成功,请将HDL文件添加到目标文件的末尾,并从列表中删除该HDL文件。 该列表被测试剩余的文件,然后发送列表中的下一个文件进行编译。 在处理列表中的所有文件之后,检查已处理的HDL文件,以便编译失败,并且如果要处理的所有HDL文件中的任何一个无法编译方法分支回到重复进程,直到所有运行成功 。

    Unrolling hardware design generate statements in a source window debugger
    3.
    发明授权
    Unrolling hardware design generate statements in a source window debugger 有权
    展开硬件设计在源窗口调试器中生成语句

    公开(公告)号:US07823097B2

    公开(公告)日:2010-10-26

    申请号:US11532216

    申请日:2006-09-15

    IPC分类号: G06F17/50

    CPC分类号: G06F17/505 G06F17/5022

    摘要: Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.

    摘要翻译: 展开硬件描述语言(“HDL”)的“生成”语句并显示展开的HDL。 对于条件生成条件进行评估。 如果声明为真,则将显示附带的HDL代码。 对于迭代生成,封闭的HDL将被显示为迭代方案边界所指定的次数。 这允许例如生成语句内声明的信号的模拟值注释,生成语句内的语义导航,并允许用户可视化目标设计中包含的内容。

    Unrolling Hardware Design Generate Statements in a Source Window Debugger
    4.
    发明申请
    Unrolling Hardware Design Generate Statements in a Source Window Debugger 有权
    展开硬件设计在源窗口生成语句调试器

    公开(公告)号:US20080072206A1

    公开(公告)日:2008-03-20

    申请号:US11532216

    申请日:2006-09-15

    IPC分类号: G06F17/50

    CPC分类号: G06F17/505 G06F17/5022

    摘要: Unrolling the “generate” statement of a hardware description language (“HDL”) and displaying the unrolled HDL. For a conditional generate the condition is evaluated. If the statement is true the enclosed HDL code will be displayed. For an iterative generate, the enclosing HDL will be displayed as many times as specified by the bounds of the iteration scheme. This allows, for example, simulation value annotations for signals declared inside the generate statement, semantic navigation inside the generate statements, and allows the user to visualize what is included in the target design.

    摘要翻译: 展开硬件描述语言(“HDL”)的“生成”语句并显示展开的HDL。 对于条件生成条件进行评估。 如果声明为真,则将显示附带的HDL代码。 对于迭代生成,封闭的HDL将被显示为迭代方案边界所指定的次数。 这允许例如生成语句内声明的信号的模拟值注释,生成语句内的语义导航,并允许用户可视化目标设计中包含的内容。

    ENHANCED STRUCTURAL REDUNDANCY DETECTION
    5.
    发明申请
    ENHANCED STRUCTURAL REDUNDANCY DETECTION 有权
    增强结构性冗余检测

    公开(公告)号:US20070266354A1

    公开(公告)日:2007-11-15

    申请号:US11382533

    申请日:2006-05-10

    IPC分类号: G06F17/50

    CPC分类号: G06F17/504

    摘要: A method for identifying isomorphic cones with sub-linear resources by exploiting reflexivities, the method comprising: identifying a gate g1 and a gate g2 in a netlist; mapping source gates of g1 with any permutation of source gates of g2 by using calls to an isomorphism detection algorithm; determining whether a permutation exists of pairings between the gates sourcing g1 and g2; resetting pairing of gates if the permutation exists; and eliminating pairwise-identical source gates of g1 and g2.

    摘要翻译: 一种用于通过利用反射性识别具有子线性资源的同构锥体的方法,所述方法包括:在网表中识别门g 1和门g 2; 通过使用对同构检测算法的调用,将g 1的源栅格映射到g 2的源极的任何排列; 确定在源出g 1和g 2之间的配对是否存在置换; 如果置换存在,重置门的配对; 并且消除了g 1和g 2的成对相同的源极。

    Method and system for predicate selection in bit-level compositional transformations
    6.
    发明申请
    Method and system for predicate selection in bit-level compositional transformations 审中-公开
    位级组合转换中谓词选择的方法和系统

    公开(公告)号:US20070168372A1

    公开(公告)日:2007-07-19

    申请号:US11333606

    申请日:2006-01-17

    IPC分类号: G06F7/00 G06F17/00

    CPC分类号: G06F17/504

    摘要: A method for performing verification includes selecting a first set containing a seed register and adding to a second set a result of a subtraction of a fanout of the first set from a fanin of the first set. A third set is rendered equal to a result of a subtraction of a fanin of the second set from a fanout of the second set, and whether a combination of the first set and the third set is equivalent to the first set is determined. In response to determining that the combination of the first set and the second set is not equivalent to the first set, a min-cut of the first set and the second set containing a minimal set of predicates between a first component and the logic to which the component fans out, wherein the logic is bordered by the second set is returned.

    摘要翻译: 一种用于执行验证的方法包括:选择包含种子寄存器的第一集合,并且从第一组的扇区中减去第一组的扇出结果,向第二组添加结果。 第三组被赋予等于从第二组的扇出中减去第二组的扇形的结果,以及第一组和第三组的组合是否等同于第一组的结果。 响应于确定第一集合和第二集合的组合不等同于第一集合,第一集合和第二集合的最小化包含第一组件和逻辑之间的最小一组谓词 组件风扇出来,其中返回逻辑与第二组相邻的逻辑。

    Method and system for predicate-based compositional minimization in a verification environment
    7.
    发明申请
    Method and system for predicate-based compositional minimization in a verification environment 失效
    在验证环境中基于谓词的组合最小化的方法和系统

    公开(公告)号:US20070106963A1

    公开(公告)日:2007-05-10

    申请号:US11249937

    申请日:2005-10-13

    IPC分类号: G06F17/50

    CPC分类号: G06F17/504

    摘要: A method for performing verification includes importing a design netlist containing one or more components and computing one or more output functions for the one or more components. One or more output equivalent state sets are generated from the one or more output functions and one or more next-state functions for the one or more components are identified. One or more image equivalent state sets for the one or more next-state functions are produced and one or more output-and-image equivalent state sets are classified for the one or more image equivalent state sets and the one or more output equivalent state sets. One or more input representatives of the one or more equivalent input sets are selected and an input map is formed from the one or more input representatives. The input map is synthesized and injected back into the netlist to generate a modified netlist.

    摘要翻译: 执行验证的方法包括导入包含一个或多个组件的设计网表,并计算一个或多个组件的一个或多个输出功能。 从一个或多个输出功能产生一个或多个输出等效状态集合,并且识别一个或多个组件的一个或多个下一个状态功能。 产生用于一个或多个下一状态函数的一个或多个图像等效状态集合,并且对于一个或多个图像等效状态集合和一个或多个输出等效状态集合分类一个或多个输出和图像等效状态集合 。 选择一个或多个等效输入集合的一个或多个输入代表,并且从一个或多个输入代表形成输入映射。 输入图合成并注入网表以生成修改的网表。