公开(公告)号：US20110019006A1

公开(公告)日：2011-01-27

申请号：US12839168

申请日：2010-07-19

申请人： Gabriel Varga ,  Greg Smith

发明人： Gabriel Varga ,  Greg Smith

IPC分类号： H04N17/00

CPC分类号： H04N17/04

摘要： In accordance with some embodiments of the invention, a video processing circuit can include a synchronization generator to generate a clock signal from an input video stream; and a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles. In accordance with some embodiments of the present invention, a video processing system may include an video input capture circuit; a video input processing circuit including a synchronization generator and a test pattern generator; a video scaling circuit; a video merging circuit to recombine the video signals provided by the video scaling circuit into one video signal; and a video output circuit including a cyclical redundancy check circuit.

摘要翻译： 根据本发明的一些实施例，视频处理电路可以包括同步发生器以从输入视频流生成时钟信号; 以及耦合以接收由所述同步发生器提供的时钟信号并且在多个周期上产生测试模式的测试模式发生器。 根据本发明的一些实施例，视频处理系统可以包括视频输入捕获电路; 包括同步发生器和测试图形发生器的视频输入处理电路; 视频缩放电路; 视频合并电路，将由视频缩放电路提供的视频信号复合成一个视频信号; 以及包括循环冗余校验电路的视频输出电路。

公开(公告)号：US07788505B2

公开(公告)日：2010-08-31

申请号：US11300542

申请日：2005-12-14

申请人： Allen J. C. Porter ,  Chun Wang ,  Kevork Kechichian ,  Gabriel Varga ,  David Strasser

发明人： Allen J. C. Porter ,  Chun Wang ,  Kevork Kechichian ,  Gabriel Varga ,  David Strasser

IPC分类号： G06F11/30

CPC分类号： G06F12/1458 ,  G06F12/1441 ,  G09G5/363 ,  G09G5/39 ,  G09G2340/02 ,  G09G2360/12 ,  H04N5/4401 ,  H04N21/4405 ,  H04N21/4408 ,  H04N21/4435

摘要： A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

摘要翻译： 图形处理器接收压缩的加密视频流。 图形处理器解密压缩的加密视频流，并将解密版本（即，解密的压缩视频流）存储在片上或片外视频存储器的受保护部分中。 然后，图形处理器允许图形处理器上的处理器和其他总线主机访问片上视频存储器，但有条件地限制对位于芯片外的其它总线主机的访问，诸如位于芯片外的耦合的中央处理单元 通过总线到图形处理器。

公开(公告)号：US20060123248A1

公开(公告)日：2006-06-08

申请号：US11300542

申请日：2005-12-14

申请人： Allen Porter ,  Chun Wang ,  Kevork Kechichian ,  Gabriel Varga ,  David Strasser

发明人： Allen Porter ,  Chun Wang ,  Kevork Kechichian ,  Gabriel Varga ,  David Strasser

IPC分类号： H04N7/16 ,  G06F11/00 ,  G06F12/14 ,  H04L9/32 ,  G06F1/26 ,  G06F17/30 ,  G08B13/00 ,  G06F11/30 ,  G06F7/04 ,  G08B21/00 ,  G06K9/00 ,  G08B29/00 ,  H03M1/68 ,  H04K1/00 ,  H04L9/00

CPC分类号： G06F12/1458 ,  G06F12/1441 ,  G09G5/363 ,  G09G5/39 ,  G09G2340/02 ,  G09G2360/12 ,  H04N5/4401 ,  H04N21/4405 ,  H04N21/4408 ,  H04N21/4435

摘要： A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

公开(公告)号：US08675076B2

公开(公告)日：2014-03-18

申请号：US12839168

申请日：2010-07-19

申请人： Gabriel Varga ,  Greg Smith

发明人： Gabriel Varga ,  Greg Smith

IPC分类号： H04N17/00 ,  H04N17/02

CPC分类号： H04N17/04

摘要： In accordance with some embodiments of the invention, a video processing circuit can include a synchronization generator to generate a clock signal from an input video stream; and a test pattern generator coupled to receive the clock signal provided by the synchronization generator and to generate a test pattern over a number of cycles. In accordance with some embodiments of the present invention, a video processing system may include an video input capture circuit; a video input processing circuit including a synchronization generator and a test pattern generator; a video scaling circuit; a video merging circuit to recombine the video signals provided by the video scaling circuit into one video signal; and a video output circuit including a cyclical redundancy check circuit.

摘要翻译： 根据本发明的一些实施例，视频处理电路可以包括同步发生器以从输入视频流生成时钟信号; 以及耦合以接收由所述同步发生器提供的时钟信号并且在多个周期上产生测试模式的测试模式发生器。 根据本发明的一些实施例，视频处理系统可以包括视频输入捕获电路; 包括同步发生器和测试图形发生器的视频输入处理电路; 视频缩放电路; 视频合并电路，将由视频缩放电路提供的视频信号复合成一个视频信号; 以及包括循环冗余校验电路的视频输出电路。

公开(公告)号：US07055038B2

公开(公告)日：2006-05-30

申请号：US09850356

申请日：2001-05-07

申请人： Allen J. C. Porter ,  Chun Wang ,  Kevork Kechichian ,  Gabriel Varga ,  David Strasser

发明人： Allen J. C. Porter ,  Chun Wang ,  Kevork Kechichian ,  Gabriel Varga ,  David Strasser

IPC分类号： G06F12/14 ,  G06T1/00 ,  H04L9/00

CPC分类号： G06F12/1458 ,  G06F12/1441 ,  G09G5/363 ,  G09G5/39 ,  G09G2340/02 ,  G09G2360/12 ,  H04N5/4401 ,  H04N21/4405 ,  H04N21/4408 ,  H04N21/4435

摘要： A graphics processor receives a compressed encrypted video stream. The graphics processor decrypts the compressed encrypted video stream and stores a decrypted version (i.e., a decrypted compressed video stream) in a protected portion of an on-chip or off-chip video memory. The graphics processor then permits processors and other bus masters on the graphics processor to access the on-chip video memory, but conditionally limits access to other bus masters that are located off-chip, such as a central processing unit located off-chip and coupled to the graphics processor via a bus.

公开(公告)号：US20050265547A1

公开(公告)日：2005-12-01

申请号：US11175882

申请日：2005-07-06

申请人： David Strasser ,  Edwin Pang ,  Gabriel Varga

发明人： David Strasser ,  Edwin Pang ,  Gabriel Varga

IPC分类号： H04L9/08 ,  H04L9/30 ,  H04N7/167 ,  H04N21/418 ,  H04N21/4367 ,  H04L9/00

CPC分类号： H04N21/4181 ,  H04L9/0841 ,  H04L9/0891 ,  H04L2209/605 ,  H04N7/1675 ,  H04N21/4367

摘要： A copy protection (CP) key used by a sending source, such as a POD, to encrypt content such as audio and/or video information is derived by a first key generator associated with a first processor and is locally encrypted by the first processor using a locally generated bus encryption key to produce a bus encrypted CP key that is sent over a local unsecure bus to a second processor, such as a graphics processor. The second processor decrypts the bus encrypted copy key using a decryption engine to obtain the CP key. The second processor receives the encrypted content and in one embodiment, also uses the same decryption engine to decrypt the encrypted content. The first and second processors locally exchange public keys to each locally derive a bus encryption key used to encrypt the CP key before it is sent over the unsecure bus and decrypt the encrypted CP key after it is sent over the bus. The locally exchanged public keys are shorter in length than those used between the CPU and POD to produce the original CP key.

摘要翻译： 由POD等发送源用于加密诸如音频和/或视频信息的内容的复制保护（CP）密钥由与第一处理器相关联的第一密钥生成器导出，并且由第一处理器本地加密使用 本地生成的总线加密密钥，以产生通过本地不安全总线发送到诸如图形处理器的第二处理器的总线加密CP密钥。 第二处理器使用解密引擎解密总线加密复制密钥以获得CP密钥。 第二处理器接收加密的内容，并且在一个实施例中，也使用相同的解密引擎来解密加密的内容。 第一和第二处理器在本机之间本地交换公共密钥本地导出用于在通过不安全总线发送之前对CP密钥进行加密的总线加密密钥，并且在通过总线发送之后解密加密的CP密钥。 本地交换的公钥的长度要比在CPU和POD之间使用的公钥短，以产生原始的CP密钥。

公开(公告)号：US5450543A

公开(公告)日：1995-09-12

申请号：US320229

申请日：1994-10-11

申请人： Gabriel Varga

发明人： Gabriel Varga

IPC分类号： G06F12/04 ,  G09G5/39 ,  G09G5/393 ,  G06F12/00

CPC分类号： G09G5/39 ,  G06F12/04 ,  G09G5/393

摘要： A memory address pointer that selects a memory location that is mapped to a video graphics circuit port is incremented only when all bytes in a memory location have been read from or written to by the host CPU. This does not depend on the order in which the host CPU reads or writes data bytes. Therefore a video controller that uses the present invention will work with 8 bit, 16 bit as well as high performance 32 bit input/output instructions.

摘要翻译： 只有存储器位置中的所有字节已被主机CPU读取或写入时，才会选择映射到视频图形电路端口的存储器位置的存储器地址指针。 这不取决于主机CPU读取或写入数据字节的顺序。 因此，使用本发明的视频控制器将使用8位，16位以及高性能32位输入/输出指令。