摘要:
Method and apparatus are presented for the generation and detection of maintenance signals in an optical data network. The maintenance signals are such that they can be read both by high bit-rate and low bit-rate receivers. Detection of the maintenance signals occurs in two stages. In a low bit-rate first stage each nodal input port is sampled in a round robin fashion to detect the presence of a maintenance signal. In a high bit-rate second stage the maintenance signal is verified and read by a high speed receiver, along with other high bit-rate information transmitted with it. One second stage high speed receiver is shared among M input channels for cost and circuit efficiency.
摘要:
Monitoring of the input power is performed on-chip and is used to monitor and maintain performance, detect failure and trigger network protection strategies. An optical power-monitoring technique uses a photodetector monolithically integrated with the semiconductor optical amplifier—Mach-Zehnder interferometer circuit to monitor the P2R device and keep the output stable while the input power varies.
摘要:
A integrated optical circuit comprises an interferometer having a first optical path and a second optical path configured for regenerating an input signal entering the first path by interference at a first coupler between continuous wave (CW) signals from the two optical paths, and a third optical path configured such that a canceling signal passing therethrough cancels, at a second coupler, a traveling signal from the first arm. When the device is operated in a counter-propagative mode, the traveling signal is the CW signal from the first arm. When the device is operated in a co-propagative mode, the traveling signal is the input signal from the first arm.
摘要:
A integrated optical circuit comprises an interferometer having a first optical path and a second optical path configured for regenerating an input signal entering the first path by interference at a first coupler between continuous wave (CW) signals from the two optical paths, and a third optical path configured such that a canceling signal passing therethrough cancels, at a second coupler, a traveling signal from the first arm. When the device is operated in a counter-propagative mode, the traveling signal is the CW signal from the first arm. When the device is operated in a co-propagative mode, the traveling signal is the input signal from the first arm.
摘要:
Monitoring of the input power is performed on-chip and is used to monitor and maintain performance, detect failure and trigger network protection strategies. An optical power-monitoring technique uses a photodetector monolithically integrated with the semiconductor optical amplifier—Mach-Zehnder interferometer circuit to monitor the P2R device and keep the output stable while the input power varies.
摘要:
A method and apparatus are disclosed to achieve a resource optimized, class of RS decoders, featuring balanced pipelined stages and parallel algorithmic components. Our RS decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for RS decoders, and can lead to reduced buffering, resulting in significant hardware savings.
摘要:
The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.
摘要:
Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it employs a combination of preemptive and non-preemptive scheduling, 4) it introduces the concept of an association array to tackle the problem of multi-rate systems (which are commonly found in multimedia applications), 5) it uses a static scheduler based on deadline-based priority levels for accurate performance estimation of a co-synthesis solution, 6) it uses a new task clustering technique which takes the changing nature of the critical path in the task graph into account, 7) it supports pipelining of task graphs to derive a cost-efficient architecture, 8) it supports a mix of various technologies, such as 5 V CMOS, 3.3 V CMOS, 2.7 V CMOS, ECL, etc., to meet embedded system constraints and minimize power dissipation, and 9) if desired, it also optimizes the architecture for power consumption.
摘要翻译:硬件 - 软件协同合成是将嵌入式系统规范分为硬件和软件模块以满足性能,功耗和成本目标的过程。 嵌入式系统一般是以非循环任务图表来表示的。 根据本发明的一个实施例,称为COSYN的共同合成算法从具有实时约束的周期性任务图开始,并且产生满足这些约束的低成本异构分布式嵌入式系统架构。 该算法具有以下特点:1)允许使用多种类型的处理元素(PE)和PE间通信链路,链路可以采用各种形式(点对点,总线,局域网等) ),2)它支持并发和顺序的通信和计算模式,3)采用抢占式和非优先级调度的组合,4)引入关联阵列的概念来解决多速率系统的问题 (通常在多媒体应用中发现),5)它使用基于截止时间优先级的静态调度器来进行合成解决方案的精确性能估计; 6)它使用新的任务聚类技术,其采用变化的性质 考虑到任务图中的关键路径,7)它支持流水线任务图以获得具有成本效益的架构,8)它支持各种技术的混合,如5 V CMOS,3.3 V CMOS,2.7 V CMOS, ECL等,以满足嵌入式 系统约束和最小化功耗,9)如果需要,它还优化了功耗的架构。
摘要:
A method and apparatus to achieve a resource optimized, class of Reed Solomon decoders, featuring balanced pipelined stages and parallel algorithmic components. The Reed Solomon decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for Reed Solomon decoders, and can lead to reduced buffering, resulting in significant hardware savings.
摘要:
A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating communication analysis graph (CAG). Partitioning communication instances to create partition clusters. Evaluating cluster statistics related to the partition clusters and assigning parameter values to the partition clusters to form a new system with new communication architecture. Reanalyzing the new system and recomputing performance metrics. If performance is improved then synthesizing CATs to realize optimized protocols. If performance is not improved then the process is repeated.