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    Multi-level power macromodeling
    1.
    发明授权
    Multi-level power macromodeling 有权

    公开(公告)号：US06625781B2

    公开(公告)日：2003-09-23

    申请号：US09771100

    申请日：2001-01-26

    申请人： Wolfgang Roethig ,  Ganesh Lakshminarayana ,  Anand Raghunathan ,  Arun Balakrishnan

    发明人： Wolfgang Roethig ,  Ganesh Lakshminarayana ,  Anand Raghunathan ,  Arun Balakrishnan

    IPC分类号： G06F1750

    CPC分类号： G06F17/5022 ,  G06F2217/78

    摘要： The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.

    Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners
    2.
    发明授权
    Methodology for the design of high-performance communication architectures for system-on-chips using communication architecture tuners 有权
    使用通信架构调谐器设计用于片上系统的高性能通信架构的方法

    公开(公告)号：US06978425B1

    公开(公告)日：2005-12-20

    申请号：US09576956

    申请日：2000-05-24

    申请人： Anand Raghunathan ,  Ganesh Lakshminarayana ,  Kanishka Lahiri ,  Sujit Dey

    发明人： Anand Raghunathan ,  Ganesh Lakshminarayana ,  Kanishka Lahiri ,  Sujit Dey

    IPC分类号： G06F9/455 ,  G06F17/50

    CPC分类号： G06F17/505

    摘要： A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating communication analysis graph (CAG). Partitioning communication instances to create partition clusters. Evaluating cluster statistics related to the partition clusters and assigning parameter values to the partition clusters to form a new system with new communication architecture. Reanalyzing the new system and recomputing performance metrics. If performance is improved then synthesizing CATs to realize optimized protocols. If performance is not improved then the process is repeated.

    摘要翻译： 一种设计通信架构的方法，包括接收分区系统，通信架构拓扑，输入轨迹和性能矩阵。 分析和创建通信分析图（CAG）。 分区通信实例来创建分区集群。 评估与分区集群相关的集群统计信息，并将参数值分配给分区集群，以形成具有新通信体系结构的新系统。 重新分析新系统并重新计算性能指标。 如果性能提高，那么合成CAT来实现优化协议。 如果性能没有改善，则重复该过程。

    Method for synthesis of common-case optimized circuits to improve performance and power dissipation
    4.
    发明授权
    Method for synthesis of common-case optimized circuits to improve performance and power dissipation 有权
    用于合成常用优化电路以提高性能和功耗的方法

    公开(公告)号：US06308313B1

    公开(公告)日：2001-10-23

    申请号：US09328897

    申请日：1999-06-09

    申请人： Ganesh Lakshminarayana ,  Anand Raghunathan ,  Kamal S. Khouri ,  Niraj K. Jha

    发明人： Ganesh Lakshminarayana ,  Anand Raghunathan ,  Kamal S. Khouri ,  Niraj K. Jha

    IPC分类号： G06F1710

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： A method for designing a circuit with reduced power consumption using a Common-Case Computation (CCC) based design. The method comprising identifying a set of common case computations from a schedule of the circuit, designing add on common detection circuit that detects the set of common case computations, designing add on common case execution circuit that executes the set of common case computations; and integrating the add on circuitry with the original circuit. A circuit design system for optimizing a circuit for power management comprising: a simulator for simulating a schedule with input traces based on a given RTL design, schedule and typical input traces; a state sequence identifier for identifying promising state sequence patterns from simulated schedules; a behavior extractor for extracting behavior corresponding to each identified state sequences; a pattern selector for choosing a best pattern; a synthesizer for synthesizing common case circuitry; and an output generator for integrating common case circuitry with an original circuit.

    摘要翻译： 使用基于共同案例计算（CCC）的设计来设计具有降低功耗的电路的方法。 所述方法包括根据所述电路的调度来识别一组常见的情况计算，设计添加检测所述一组常规情况计算的公共检测电路，在执行所述一组通用案例计算的公共案例执行电路上进行设计; 并将加电电路与原始电路集成。 一种用于优化用于电力管理的电路的电路设计系统，包括：用于基于给定的RTL设计，时间表和典型输入轨迹来模拟具有输入轨迹的调度的模拟器; 用于从模拟时间表识别有希望的状态序列模式的状态序列标识符; 用于提取与每个识别的状态序列相对应的行为的行为提取器; 用于选择最佳图案的图案选择器; 用于合成公用案例电路的合成器; 以及用于将公共壳体电路与原始电路集成的输出发生器。

    Common case optimized circuit structure for high-performance and low-power VLSI designs
    5.
    发明授权
    Common case optimized circuit structure for high-performance and low-power VLSI designs 有权
    用于高性能和低功耗VLSI设计的通用案例优化电路结构

    公开(公告)号：US06275969B1

    公开(公告)日：2001-08-14

    申请号：US09328896

    申请日：1999-06-09

    申请人： Ganesh Lakshminarayana ,  Anand Raghunathan

    发明人： Ganesh Lakshminarayana ,  Anand Raghunathan

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： This present invention presents a Common Case Computation (CCC) based design. A computation circuit with reduced power consumption, said computation circuit having a plurality of components. The components include a general purpose circuit, a common case detection circuit and a common case execution circuit. The common case detection circuit detects an occurrence of a common case based on a first subset of primary inputs and a first subset of internal variables for the general purpose circuit, and the common case execution circuit computes a subset of primary outputs of the general purpose circuit based on a second subset of primary inputs for the general purpose circuits and a second subset of internal variables for the general purpose circuit. The first subset of the primary inputs and the first subset of internal variables can be the same as the second subset of primary variables and the second subset of internal variables respectively. The common case computation circuit identifies and exploits common case computations during the design process for reducing power consumption.

    摘要翻译： 本发明提出了一种基于通用案例计算（CCC）的设计。 一种功耗降低的计算电路，所述计算电路具有多个部件。 这些组件包括通用电路，公用案例检测电路和公用案例执行电路。 通用情况检测电路基于通用电路的主要输入的第一子集和内部变量的第一子集来检测公共情况的发生，并且公共情况执行电路计算通用电路的主要输出的子集 基于用于通用电路的主要输入的第二子集和用于通用电路的内部变量的第二子集。 主要输入的第一个子集和内​​部变量的第一个子集可以分别与主变量的第二个子集和内​​部变量的第二个子集相同。 常用案例计算电路在设计过程中识别和利用常见的案例计算，以降低功耗。

    Constrained register sharing technique for low power VLSI design
    7.
    发明授权
    Constrained register sharing technique for low power VLSI design 失效
    低功耗VLSI设计的约束寄存器共享技术

    公开(公告)号：US06195786B1

    公开(公告)日：2001-02-27

    申请号：US09089388

    申请日：1998-06-03

    申请人： Anand Raghunathan ,  Sujit Dey ,  Ganesh Lakshminarayana ,  Niraj K. Jha

    发明人： Anand Raghunathan ,  Sujit Dey ,  Ganesh Lakshminarayana ,  Niraj K. Jha

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045 ,  G06F2217/78

    摘要： A power management method and system targeted toward high-level synthesis of data-dominated behavioral descriptions. The method of the present invention is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, a procedure for constraining variable assignment is provided so that the functional units in the synthesized architecture do not execute any spurious operations.

    摘要翻译： 一种面向数据主导行为描述的高级综合的电源管理方法和系统。 本发明的方法是基于可变分配可以显着影响合成架构中的功率管理机会的观察。 基于该观察，提供了约束变量分配的过程，使得合成架构中的功能单元不执行任何虚假操作。

    REED SOLOMON DECODING OF SIGNALS HAVING VARIABLE INPUT DATA RATES
    8.
    发明申请
    REED SOLOMON DECODING OF SIGNALS HAVING VARIABLE INPUT DATA RATES 有权
    具有可变输入数据速率的信号的REED SOLOMON解码

    公开(公告)号：US20070300137A1

    公开(公告)日：2007-12-27

    申请号：US11755614

    申请日：2007-05-30

    申请人： Ganesh Lakshminarayana ,  Jayanta Das

    发明人： Ganesh Lakshminarayana ,  Jayanta Das

    IPC分类号： H03M13/00

    CPC分类号： H03M13/1555 ,  H03M13/1515 ,  H03M13/1595 ,  H03M13/6561

    摘要： A method and apparatus are disclosed to achieve a resource optimized, class of RS decoders, featuring balanced pipelined stages and parallel algorithmic components. Our RS decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for RS decoders, and can lead to reduced buffering, resulting in significant hardware savings.

    摘要翻译： 公开了一种方法和装置，以实现资源优化的一类RS解码器，其具有平衡流水线级和并行算法组件。 我们的RS解码器有两个流水线阶段，一个阶段执行校正子计算，第二个阶段实现错误定位器多项式评估，错误定位和纠错。 由于第二流水线阶段执行若干任务，这些任务可以彼此共享资源，从而实现紧凑的实现。 此外，我们提出了一种可以用于计算两个关键算法组件（校正子计算，错误定位）所需的并行级别的技术，以便RS解码器可以处理可变速率的输入，以最小的延迟和资源消耗。 我们表明，低延迟本身是RS解码器的重要考虑因素，可以减少缓冲，从而节省大量的硬件。

    Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems
    10.
    发明授权
    Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems 失效
    基于调度的异构分布式嵌入式系统的硬件 - 软件协同合成

    公开(公告)号：US6112023A

    公开(公告)日：2000-08-29

    申请号：US24604

    申请日：1998-02-17

    申请人： Bharat P. Dave ,  Niraj K. Jha ,  Ganesh Lakshminarayana

    发明人： Bharat P. Dave ,  Niraj K. Jha ,  Ganesh Lakshminarayana

    IPC分类号： G06F9/48 ,  G06F17/50 ,  G06F9/44

    CPC分类号： G06F9/4887 ,  G06F17/5045 ,  G06F2217/78 ,  Y02B60/144

    摘要： Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it employs a combination of preemptive and non-preemptive scheduling, 4) it introduces the concept of an association array to tackle the problem of multi-rate systems (which are commonly found in multimedia applications), 5) it uses a static scheduler based on deadline-based priority levels for accurate performance estimation of a co-synthesis solution, 6) it uses a new task clustering technique which takes the changing nature of the critical path in the task graph into account, 7) it supports pipelining of task graphs to derive a cost-efficient architecture, 8) it supports a mix of various technologies, such as 5 V CMOS, 3.3 V CMOS, 2.7 V CMOS, ECL, etc., to meet embedded system constraints and minimize power dissipation, and 9) if desired, it also optimizes the architecture for power consumption.

    摘要翻译： 硬件 - 软件协同合成是将嵌入式系统规范分为硬件和软件模块以满足性能，功耗和成本目标的过程。 嵌入式系统一般是以非循环任务图表来表示的。 根据本发明的一个实施例，称为COSYN的共同合成算法从具有实时约束的周期性任务图开始，并且产生满足这些约束的低成本异构分布式嵌入式系统架构。 该算法具有以下特点：1）允许使用多种类型的处理元素（PE）和PE间通信链路，链路可以采用各种形式（点对点，总线，局域网等） ），2）它支持并发和顺序的通信和计算模式，3）采用抢占式和非优先级调度的组合，4）引入关联阵列的概念来解决多速率系统的问题 （通常在多媒体应用中发现），5）它使用基于截止时间优先级的静态调度器来进行合成解决方案的精确性能估计; 6）它使用新的任务聚类技术，其采用变化的性质 考虑到任务图中的关键路径，7）它支持流水线任务图以获得具有成本效益的架构，8）它支持各种技术的混合，如5 V CMOS，3.3 V CMOS，2.7 V CMOS， ECL等，以满足嵌入式 系统约束和最小化功耗，9）如果需要，它还优化了功耗的架构。