-
1.发明申请公开(公告)号：US20070300137A1
公开(公告)日：2007-12-27
申请号：US11755614
申请日：2007-05-30
IPC分类号： H03M13/00
CPC分类号： H03M13/1555 , H03M13/1515 , H03M13/1595 , H03M13/6561
摘要： A method and apparatus are disclosed to achieve a resource optimized, class of RS decoders, featuring balanced pipelined stages and parallel algorithmic components. Our RS decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for RS decoders, and can lead to reduced buffering, resulting in significant hardware savings.
摘要翻译： 公开了一种方法和装置，以实现资源优化的一类RS解码器，其具有平衡流水线级和并行算法组件。 我们的RS解码器有两个流水线阶段，一个阶段执行校正子计算，第二个阶段实现错误定位器多项式评估，错误定位和纠错。 由于第二流水线阶段执行若干任务，这些任务可以彼此共享资源，从而实现紧凑的实现。 此外，我们提出了一种可以用于计算两个关键算法组件（校正子计算，错误定位）所需的并行级别的技术，以便RS解码器可以处理可变速率的输入，以最小的延迟和资源消耗。 我们表明，低延迟本身是RS解码器的重要考虑因素，可以减少缓冲，从而节省大量的硬件。
-
2.发明授权公开(公告)号：US07987412B2
公开(公告)日：2011-07-26
申请号：US11755614
申请日：2007-05-30
IPC分类号： H03M13/00
CPC分类号： H03M13/1555 , H03M13/1515 , H03M13/1595 , H03M13/6561
摘要： A method and apparatus to achieve a resource optimized, class of Reed Solomon decoders, featuring balanced pipelined stages and parallel algorithmic components. The Reed Solomon decoder has two pipeline stages, with one stage implementing syndrome computation and the second stage implementing error locator polynomial evaluation, error location and error correction. Since the second pipeline stage performs several tasks, these tasks can share resources with each other, resulting in a compact implementation. In addition, we present a technique that can be used to compute the level of parallelism required of two key algorithmic components (syndrome computation, error location) so that the RS decoder can handle inputs of variable rates, with minimal latency and resource consumption. We show that low latency, in itself, is an important consideration for Reed Solomon decoders, and can lead to reduced buffering, resulting in significant hardware savings.
摘要翻译： 一种实现资源优化的Reed Solomon解码器的方法和装置，具有平衡流水线阶段和并行算法组件。 Reed Solomon解码器有两个流水线阶段，一个阶段实施了校正子计算，第二个阶段实现了误差定位多项式评估，误差定位和纠错。 由于第二流水线阶段执行若干任务，这些任务可以彼此共享资源，从而实现紧凑的实现。 此外，我们提出了一种可以用于计算两个关键算法组件（校正子计算，错误定位）所需的并行级别的技术，以便RS解码器可以处理可变速率的输入，以最小的延迟和资源消耗。 我们表明，低延迟本身就是Reed Solomon解码器的重要考虑因素，可以减少缓冲，从而节省大量的硬件。
-
3.发明授权公开(公告)号：US07190909B2
公开(公告)日：2007-03-13
申请号：US10172369
申请日：2002-06-14
申请人： Jayanta Das , Ganesh Lakshminarayana , Kuo-Ming Lee , Roman Antosik , Scott Kaminski , Jithamithra Sarathy , Boris Stefanov , Ronald Simprini , Bharat Dave
发明人： Jayanta Das , Ganesh Lakshminarayana , Kuo-Ming Lee , Roman Antosik , Scott Kaminski , Jithamithra Sarathy , Boris Stefanov , Ronald Simprini , Bharat Dave
IPC分类号： H04B10/00
CPC分类号： H04B10/0775 , H04B2210/078
摘要： Method and apparatus are presented for the generation and detection of maintenance signals in an optical data network. The maintenance signals are such that they can be read both by high bit-rate and low bit-rate receivers. Detection of the maintenance signals occurs in two stages. In a low bit-rate first stage each nodal input port is sampled in a round robin fashion to detect the presence of a maintenance signal. In a high bit-rate second stage the maintenance signal is verified and read by a high speed receiver, along with other high bit-rate information transmitted with it. One second stage high speed receiver is shared among M input channels for cost and circuit efficiency.
摘要翻译： 提出了用于在光数据网络中生成和检测维护信号的方法和装置。 维护信号使得它们可以被高比特率和低比特率接收机读取。 维护信号的检测分两个阶段进行。 在低比特率第一级中，每个节点输入端口以循环方式进行采样以检测维护信号的存在。 在高比特率第二级中，维护信号与高速接收机一起被验证和读取，以及与其一起发送的其他高比特率信息。 一个第二级高速接收机在M个输入通道之间共享成本和电路效率。
-
4.发明授权公开(公告)号：US07319555B2
公开(公告)日：2008-01-15
申请号：US11412435
申请日：2006-04-27
IPC分类号： H01S3/00
CPC分类号： H04B10/0775 , H04B10/0777
摘要： Monitoring of the input power is performed on-chip and is used to monitor and maintain performance, detect failure and trigger network protection strategies. An optical power-monitoring technique uses a photodetector monolithically integrated with the semiconductor optical amplifier—Mach-Zehnder interferometer circuit to monitor the P2R device and keep the output stable while the input power varies.
摘要翻译： 输入功率的监控是片内执行的，用于监控和维护性能，检测故障并触发网络保护策略。 光功率监测技术使用与半导体光放大器 - 马赫 - 策德尔干涉仪电路单片集成的光电检测器来监测P2R器件，并在输入功率变化时保持输出稳定。
-
公开(公告)号：US06625781B2
公开(公告)日：2003-09-23
申请号：US09771100
申请日：2001-01-26
IPC分类号： G06F1750
CPC分类号： G06F17/5022 , G06F2217/78
摘要： The invention utilizes the linear complexity of orthogonal vectors to reduce the number of equations (or variables) to be solved. The present invention constructs a power model of a set of combinations of states without considering irrelevant combinations. The invention distinguishes between the switching direction on the input and the output pin. The invention considers state-dependency as a function of power consumed and depending on the paths through internal nodes. The model considers switching input pins that do not cause the output pin to switch to overcome inaccuracies caused by combining the power pin model with the state and arc power model with state. The model considers switching input pins that cause the output pin to switch. For cells in which the slewrate propagation effect from input to output is negligible, the invention uses a model of 2 power pins with state. The invention also determines the validity of this model. The present invention also models a power arc from one input pin to multiple output pins.
-
6.发明授权Scheduling-based hardware-software co-synthesis of heterogeneous distributed embedded systems 失效基于调度的异构分布式嵌入式系统的硬件 - 软件协同合成
公开(公告)号：US6112023A
公开(公告)日：2000-08-29
申请号：US24604
申请日：1998-02-17
CPC分类号： G06F9/4887 , G06F17/5045 , G06F2217/78 , Y02B60/144
摘要： Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, and cost goals. Embedded systems are generally specified in terms of a set of acyclic task graphs. According to one embodiment of the present invention, a co-synthesis algorithm, called COSYN, starts with periodic task graphs with real-time constraints and produces a low-cost heterogeneous distributed embedded system architecture meeting these constraints. The algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and inter-PE communication links, where the links can take various forms (point-to-point, bus, local area network, etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it employs a combination of preemptive and non-preemptive scheduling, 4) it introduces the concept of an association array to tackle the problem of multi-rate systems (which are commonly found in multimedia applications), 5) it uses a static scheduler based on deadline-based priority levels for accurate performance estimation of a co-synthesis solution, 6) it uses a new task clustering technique which takes the changing nature of the critical path in the task graph into account, 7) it supports pipelining of task graphs to derive a cost-efficient architecture, 8) it supports a mix of various technologies, such as 5 V CMOS, 3.3 V CMOS, 2.7 V CMOS, ECL, etc., to meet embedded system constraints and minimize power dissipation, and 9) if desired, it also optimizes the architecture for power consumption.
摘要翻译： 硬件 - 软件协同合成是将嵌入式系统规范分为硬件和软件模块以满足性能，功耗和成本目标的过程。 嵌入式系统一般是以非循环任务图表来表示的。 根据本发明的一个实施例，称为COSYN的共同合成算法从具有实时约束的周期性任务图开始，并且产生满足这些约束的低成本异构分布式嵌入式系统架构。 该算法具有以下特点：1）允许使用多种类型的处理元素（PE）和PE间通信链路，链路可以采用各种形式（点对点，总线，局域网等） ），2）它支持并发和顺序的通信和计算模式，3）采用抢占式和非优先级调度的组合，4）引入关联阵列的概念来解决多速率系统的问题 （通常在多媒体应用中发现），5）它使用基于截止时间优先级的静态调度器来进行合成解决方案的精确性能估计; 6）它使用新的任务聚类技术，其采用变化的性质 考虑到任务图中的关键路径，7）它支持流水线任务图以获得具有成本效益的架构，8）它支持各种技术的混合，如5 V CMOS，3.3 V CMOS，2.7 V CMOS， ECL等，以满足嵌入式 系统约束和最小化功耗，9）如果需要，它还优化了功耗的架构。
-
7.发明授权公开(公告)号：US06978425B1
公开(公告)日：2005-12-20
申请号：US09576956
申请日：2000-05-24
CPC分类号： G06F17/505
摘要： A method of designing a communication architecture comprising receiving a partitioned system, communication architecture topology, input traces and performance matrices. Analyzing and creating communication analysis graph (CAG). Partitioning communication instances to create partition clusters. Evaluating cluster statistics related to the partition clusters and assigning parameter values to the partition clusters to form a new system with new communication architecture. Reanalyzing the new system and recomputing performance metrics. If performance is improved then synthesizing CATs to realize optimized protocols. If performance is not improved then the process is repeated.
摘要翻译： 一种设计通信架构的方法，包括接收分区系统，通信架构拓扑，输入轨迹和性能矩阵。 分析和创建通信分析图（CAG）。 分区通信实例来创建分区集群。 评估与分区集群相关的集群统计信息，并将参数值分配给分区集群，以形成具有新通信体系结构的新系统。 重新分析新系统并重新计算性能指标。 如果性能提高，那么合成CAT来实现优化协议。 如果性能没有改善，则重复该过程。
-
公开(公告)号：US07239768B2
公开(公告)日：2007-07-03
申请号：US11142924
申请日：2005-06-02
CPC分类号： H04B10/299 , G02B6/12007 , G02F1/3517 , G02F2001/217 , G02F2002/006
摘要： A integrated optical circuit comprises an interferometer having a first optical path and a second optical path configured for regenerating an input signal entering the first path by interference at a first coupler between continuous wave (CW) signals from the two optical paths, and a third optical path configured such that a canceling signal passing therethrough cancels, at a second coupler, a traveling signal from the first arm. When the device is operated in a counter-propagative mode, the traveling signal is the CW signal from the first arm. When the device is operated in a co-propagative mode, the traveling signal is the input signal from the first arm.
摘要翻译： 集成光电路包括具有第一光路和第二光路的干涉仪，其被配置用于通过来自两个光路的连续波（CW）信号之间的第一耦合器处的干扰再现进入第一路径的输入信号，以及第三光路 路径被配置为使得通过的抵消信号在第二耦合器处抵消来自第一臂的行进信号。 当设备以反向传播模式操作时，行进信号是来自第一臂的CW信号。 当设备以共同传播模式操作时，行进信号是来自第一臂的输入信号。
-
9.发明授权公开(公告)号：US06735744B2
公开(公告)日：2004-05-11
申请号：US10013496
申请日：2001-12-13
申请人： Anand Raghunathan , Ganesh Lakshminarayana , Nachiketh Potlapally , Michael S. Hsiao , Srimat T. Chakradhar
发明人： Anand Raghunathan , Ganesh Lakshminarayana , Nachiketh Potlapally , Michael S. Hsiao , Srimat T. Chakradhar
IPC分类号： G06F1750
CPC分类号： G06F17/5022
摘要： A method of creating models for power estimation of a circuit comprising generating an input space for the circuit. The input space is separated into multiple power modes corresponding to regions that display similar power behavior. Separate power models are generated for each of said multiple power modes. A power mode identification function is created that selects an appropriate power model from the separate power models based on the present and past values of the circuit inputs.
摘要翻译： 一种创建用于电路的功率估计的模型的方法，包括产生用于所述电路的输入空间。 输入空间分为多个功率模式，对应于显示类似功率行为的区域。 对于所述多个功率模式中的每一个产生分离的功率模型。 创建功率模式识别功能，其基于电路输入的当前和过去值，从单独的功率模型中选择适当的功率模型。
-
10.发明授权Method for synthesis of common-case optimized circuits to improve performance and power dissipation 有权用于合成常用优化电路以提高性能和功耗的方法公开(公告)号：US06308313B1
公开(公告)日：2001-10-23
申请号：US09328897
申请日：1999-06-09
IPC分类号： G06F1710
CPC分类号： G06F17/5045 , G06F2217/78
摘要： A method for designing a circuit with reduced power consumption using a Common-Case Computation (CCC) based design. The method comprising identifying a set of common case computations from a schedule of the circuit, designing add on common detection circuit that detects the set of common case computations, designing add on common case execution circuit that executes the set of common case computations; and integrating the add on circuitry with the original circuit. A circuit design system for optimizing a circuit for power management comprising: a simulator for simulating a schedule with input traces based on a given RTL design, schedule and typical input traces; a state sequence identifier for identifying promising state sequence patterns from simulated schedules; a behavior extractor for extracting behavior corresponding to each identified state sequences; a pattern selector for choosing a best pattern; a synthesizer for synthesizing common case circuitry; and an output generator for integrating common case circuitry with an original circuit.
摘要翻译： 使用基于共同案例计算（CCC）的设计来设计具有降低功耗的电路的方法。 所述方法包括根据所述电路的调度来识别一组常见的情况计算，设计添加检测所述一组常规情况计算的公共检测电路，在执行所述一组通用案例计算的公共案例执行电路上进行设计; 并将加电电路与原始电路集成。 一种用于优化用于电力管理的电路的电路设计系统，包括：用于基于给定的RTL设计，时间表和典型输入轨迹来模拟具有输入轨迹的调度的模拟器; 用于从模拟时间表识别有希望的状态序列模式的状态序列标识符; 用于提取与每个识别的状态序列相对应的行为的行为提取器; 用于选择最佳图案的图案选择器; 用于合成公用案例电路的合成器; 以及用于将公共壳体电路与原始电路集成的输出发生器。
-
-
-
-
-
-
-
-
-
搜索结果
15 条记录 (耗时 0.018 秒)
