公开(公告)号：US20070109865A1

公开(公告)日：2007-05-17

申请号：US11527375

申请日：2006-09-25

申请人： Gary Maki ,  Jody Gambles ,  Sterling Whitaker

发明人： Gary Maki ,  Jody Gambles ,  Sterling Whitaker

IPC分类号： G11C11/34

CPC分类号： G11C11/4125 ,  H03K19/00338

摘要： A system has a reduced sensitivity to Single Event Upset and/or Single Event Transient(s) compared to traditional logic devices. In a particular embodiment, the system includes an input, a logic block, a bias stage, a state machine, and an output. The logic block is coupled to the input. The logic block is for implementing a logic function, receiving a data set via the input, and generating a result f by applying the data set to the logic function. The bias stage is coupled to the logic block. The bias stage is for receiving the result from the logic block and presenting it to the state machine. The state machine is coupled to the bias stage. The state machine is for receiving, via the bias stage, the result generated by the logic block. The state machine is configured to retain a state value for the system. The state value is typically based on the result generated by the logic block. The output is coupled to the state machine. The output is for providing the value stored by the state machine. Some embodiments of the invention produce dual rail outputs Q and Q′. The logic block typically contains combinational logic and is similar, in size and transistor configuration, to a conventional CMOS combinational logic design. However, only a very small portion of the circuits of these embodiments, is sensitive to Single Event Upset and/or Single Event Transients.

摘要翻译： 与传统逻辑器件相比，系统对单事件颠簸和/或单事件瞬态的灵敏度降低。 在特定实施例中，系统包括输入，逻辑块，偏置级，状态机和输出。 逻辑块耦合到输入端。 逻辑块用于实现逻辑功能，经由输入接收数据集，并通过将数据集应用于逻辑函数来生成结果f。 偏置级耦合到逻辑块。 偏置阶段用于从逻辑块接收结果并将其呈现给状态机。 状态机耦合到偏置级。 状态机用于通过偏置级接收由逻辑块产生的结果。 状态机配置为保留系统的状态值。 状态值通常基于由逻辑块生成的结果。 输出耦合到状态机。 输出用于提供状态机存储的值。 本发明的一些实施例产生双轨输出Q和Q'。 逻辑块通常包含组合逻辑，并且在尺寸和晶体管配置中与传统的CMOS组合逻辑设计类似。 然而，这些实施例的电路中只有很小一部分对单事件不正常和/或单事件瞬变敏感。

公开(公告)号：US06573773B2

公开(公告)日：2003-06-03

申请号：US09776453

申请日：2001-02-02

申请人： Gary Maki ,  Kenneth Haas ,  Shi Quan ,  James Murguia

发明人： Gary Maki ,  Kenneth Haas ,  Shi Quan ,  James Murguia

IPC分类号： H03K312

CPC分类号： H03K3/0375

摘要： A Single Event Upset (SEU) resistant latch circuit that uses the Single Event Resistant Topology (SERT) comprises a first circuit module electrically coupled to a second circuit module. In the SERT-1 embodiment, the first circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. The second circuit module has two output terminals, including four cross-coupled p-channel (PMOS) transistors coupled with two n-channel (NMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-1 State Table. In the SERT-2 embodiment, the first circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. The second circuit module has two output terminals, including four cross-coupled n-channel (NMOS) transistors coupled with two p-channel (PMOS) transistors. These four output terminals satisfy a set of state equations that can be used to obtain the SERT-2 State Table.

摘要翻译： 使用单事件阻抗拓扑（SERT）的单事件颠覆（SEU）阻止锁存电路包括电耦合到第二电路模块的第一电路模块。 在SERT-1实施例中，第一电路模块具有两个输出端，包括与两个n沟道（NMOS）晶体管耦合的四个交叉耦合p沟道（PMOS）晶体管。 第二电路模块具有两个输出端，包括与两个n沟道（NMOS）晶体管耦合的四个交叉耦合p沟道（PMOS）晶体管。 这四个输出端子满足可用于获得SERT-1状态表的一组状态方程。 在SERT-2实施例中，第一电路模块具有两个输出端，包括与两个p沟道（PMOS）晶体管耦合的四个交叉耦合的n沟道（NMOS）晶体管。 第二电路模块具有两个输出端，包括与两个p沟道（PMOS）晶体管耦合的四个交叉耦合的n沟道（NMOS）晶体管。 这四个输出端子满足可用于获得SERT-2状态表的一组状态方程。