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    Print engine having authentication device for preventing multi-word memory writing upon power drop
    1.
    发明授权
    Print engine having authentication device for preventing multi-word memory writing upon power drop 有权
    具有用于在掉电时防止多字存储器写入的认证装置的打印引擎

    公开(公告)号：US07747887B2

    公开(公告)日：2010-06-29

    申请号：US11749750

    申请日：2007-05-16

    Applicant: Gary Shipton ,  Simon Robert Walmsley

    Inventor： Gary Shipton ,  Simon Robert Walmsley

    IPC: G06F1/30

    CPC classification number: G06F21/73 ,  B41J2/04505 ,  B41J2/04508 ,  B41J2/0451 ,  B41J2/04528 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/04563 ,  B41J2/04573 ,  B41J2/04586 ,  B41J2202/20 ,  G06F21/554 ,  G06F21/57 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/74 ,  G06F21/75 ,  G06F21/78 ,  H03K5/1252 ,  H04N1/405 ,  Y10S707/99933 ,  Y10S707/99939 ,  Y10T29/49401

    Abstract: A print engine comprising at least one print controller and at least one associated authentication device is provided. Each authentication device has a processor, non-volatile memory, an input for receiving power from a power supply and a power detection unit. Each authentication device is configured to enable multi-word writes to the non-volatile memory under control of the associated print controller. The processor is configured to control and trim the amount of power supplied to the input to predetermine a threshold at which operation of the authentication device is established. The power detection unit is configured to monitor a voltage level of the power supplied to the input, and in the event the voltage level drops below the predetermined threshold, preventing subsequent words in any multi-word write currently being performed from being written to the memory.

    Abstract translation: 提供了包括至少一个打印控制器和至少一个相关联的认证装置的打印引擎。 每个认证设备具有处理器，非易失性存储器，用于从电源和功率检测单元接收电力的输入。 每个认证设备被配置为在相关联的打印控制器的控制下启用对非易失性存储器的多字写入。 处理器被配置为控制和修剪提供给输入的功率量，以预先确定认证装置的操作建立的阈值。 电源检测单元被配置为监视提供给输入的电力的电压电平，并且在电压电平降低到预定阈值以下的情况下，防止当前正在执行的任何多字写入中的后续字被写入存储器 。

    Method of controlling clock signal
    4.
    发明授权
    Method of controlling clock signal 失效
    控制时钟信号的方法

    公开(公告)号：US08005636B2

    公开(公告)日：2011-08-23

    申请号：US12564045

    申请日：2009-09-21

    Applicant: Gary Shipton ,  Simon Robert Walmsley

    Inventor： Gary Shipton ,  Simon Robert Walmsley

    IPC: G06F19/00

    CPC classification number: G06F21/73 ,  B41J2/04505 ,  B41J2/04508 ,  B41J2/0451 ,  B41J2/04528 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/04563 ,  B41J2/04573 ,  B41J2/04586 ,  B41J2202/20 ,  G06F21/554 ,  G06F21/57 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/74 ,  G06F21/75 ,  G06F21/78 ,  H03K5/1252 ,  H04N1/405 ,  Y10S707/99933 ,  Y10S707/99939 ,  Y10T29/49401

    Abstract: A method of controlling a clock signal with a print controller is provided. In response to receiving an external signal, the print controller determines the number of cycles of a clock signal generated by a ring oscillator of the print controller during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and outputs the determined number of cycles to an external circuit. In response to receiving a trim value from clock trim circuitry of the print controller which trims the frequency of the clock signal based on the determined number of cycles from the external circuit, the trim value is stored in memory of the print controller. The clock trim circuitry is controlled to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

    Abstract translation: 提供了一种利用打印控制器控制时钟信号的方法。 响应于接收到外部信号，打印控制器在外部信号的预定数量的周期内或由外部信号的周期数量决定由打印控制器的环形振荡器产生的时钟信号的周期数 时钟信号的预定次数，并将所确定的周期数输出到外部电路。 响应于从打印控制器的时钟调整电路接收到修剪值，该修剪值基于从外部电路确定的周期数来修正时钟信号的频率，修整值被存储在打印控制器的存储器中。 时钟调整电路被控制以利用修整值来修整由环形振荡器产生的时钟信号的频率。

    Method Of Controlling Quality For A Print Controller
    5.
    发明申请
    Method Of Controlling Quality For A Print Controller 失效
    控制打印控制器质量的方法

    公开(公告)号：US20080086655A1

    公开(公告)日：2008-04-10

    申请号：US11951213

    申请日：2007-12-05

    Applicant: Gary Shipton ,  Simon Walmsley

    Inventor： Gary Shipton ,  Simon Walmsley

    IPC: G06F1/08 ,  G06F12/02

    CPC classification number: G06F21/73 ,  B41J2/04505 ,  B41J2/04508 ,  B41J2/0451 ,  B41J2/04528 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/04563 ,  B41J2/04573 ,  B41J2/04586 ,  B41J2202/20 ,  G06F21/554 ,  G06F21/57 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/74 ,  G06F21/75 ,  G06F21/78 ,  H03K5/1252 ,  H04N1/405 ,  Y10S707/99933 ,  Y10S707/99939 ,  Y10T29/49401

    Abstract: A method performed by a quality assurance integrated circuit for a print controller, the quality assurance integrated circuit comprising a memory; a system clock for generating a clock signal; clock trim circuitry for trimming the frequency of the clock signal; and a processor. the method includes, in the processor, in response to receiving an external signal, determining the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit; and in response to receiving a trim value based on the determined number of cycles from the external circuit, storing the trim value in the memory and controlling the clock trim circuitry to trim the frequency of the clock signal using the trim value.

    Abstract translation: 一种由打印控制器的质量保证集成电路执行的方法，所述质量保证集成电路包括存储器; 用于产生时钟信号的系统时钟; 时钟调整电路，用于调整时钟信号的频率; 和处理器。 该方法在处理器中包括响应于接收到外部信号，在预定数量的周期期间在外部信号的预定数量周期内确定时钟信号的周期数或外部信号的周期数 并将确定的周期数输出到外部电路; 并且响应于基于来自外部电路的确定的周期数接收修整值，将修整值存储在存储器中，并且使用修整值来控制时钟修整电路以修整时钟信号的频率。

    Integrated circuit having clock trim circuitry
    6.
    发明授权
    Integrated circuit having clock trim circuitry 有权
    具有时钟微调电路的集成电路

    公开(公告)号：US07171323B2

    公开(公告)日：2007-01-30

    申请号：US11212702

    申请日：2005-08-29

    Applicant: Gary Shipton ,  Simon Robert Walmsley

    Inventor： Gary Shipton ,  Simon Robert Walmsley

    IPC: G06F19/00 ,  G11C8/18 ,  G01R35/00

    CPC classification number: G06F21/73 ,  B41J2/04505 ,  B41J2/04508 ,  B41J2/0451 ,  B41J2/04528 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/04563 ,  B41J2/04573 ,  B41J2/04586 ,  B41J2202/20 ,  G06F21/554 ,  G06F21/57 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/74 ,  G06F21/75 ,  G06F21/78 ,  H03K5/1252 ,  H04N1/405 ,  Y10S707/99933 ,  Y10S707/99939 ,  Y10T29/49401

    Abstract: An integrated circuit is provided comprising a processor, an onboard system clock having a ring oscillator for generating a clock signal, a memory, and clock trim circuitry. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock signal during a predetermined number of cycles of the external signal or the number of cycles of the external signal during a predetermined number of cycles of the clock signal and to output the determined number of cycles to an external circuit. The processor is also arranged to, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

    Abstract translation: 提供了一种集成电路，其包括处理器，具有用于产生时钟信号的环形振荡器的板载系统时钟，存储器和时钟微调电路。 处理器被布置为响应于接收到外部信号，在外部信号的预定数量的周期期间或者在外部信号的预定次数周期期间确定时钟信号的周期数 并将所确定的周期数输出到外部电路。 处理器还被布置为响应于基于从外部电路确定的周期数接收到修整值，将修整值存储在存储器中并且控制时钟修整电路以修整由该电路产生的时钟信号的频率 环形振荡器使用修整值。

    Quality assurance IC having clock trimmer
    7.
    发明申请
    Quality assurance IC having clock trimmer 失效
    质量保证IC具有时钟微调器

    公开(公告)号：US20060259258A1

    公开(公告)日：2006-11-16

    申请号：US11488841

    申请日：2006-07-19

    Applicant: Gary Shipton ,  Simon Walmsley

    Inventor： Gary Shipton ,  Simon Walmsley

    IPC: G06F19/00

    CPC classification number: G06F21/73 ,  B41J2/04505 ,  B41J2/04508 ,  B41J2/0451 ,  B41J2/04528 ,  B41J2/04541 ,  B41J2/04543 ,  B41J2/04563 ,  B41J2/04573 ,  B41J2/04586 ,  B41J2202/20 ,  G06F21/554 ,  G06F21/57 ,  G06F21/575 ,  G06F21/64 ,  G06F21/71 ,  G06F21/74 ,  G06F21/75 ,  G06F21/78 ,  H03K5/1252 ,  H04N1/405 ,  Y10S707/99933 ,  Y10S707/99939 ,  Y10T29/49401

    Abstract: A quality assurance integrated circuit for a print controller is provided. The IC has a memory, a system clock having a ring oscillator for generating a clock signal, clock trim circuitry for trimming the clock signal generated by the system clock and a processor. The processor is arranged to, in response to receiving an external signal, determine the number of cycles of the clock or external signal during a predetermined number of cycles of the external or clock signal, respectively and to output the determined number of cycles to an external circuit, and, in response to receiving a trim value based on the determined number of cycles from the external circuit, store the trim value in the memory and control the clock trim circuitry to trim the frequency of the clock signal generated by the ring oscillator using the trim value.

    Abstract translation: 提供了一种用于打印控制器的质量保证集成电路。 IC具有存储器，具有用于产生时钟信号的环形振荡器的系统时钟，用于调整由系统时钟产生的时钟信号的时钟调整电路和处理器。 处理器被布置为响应于接收到外部信号，在外部或时钟信号的预定数量的周期期间分别确定时钟或外部信号的周期数，并将确定的周期数输出到外部 电路，并且响应于基于从外部电路确定的周期数接收到修整值，将修整值存储在存储器中并且控制时钟修整电路以修整由环形振荡器产生的时钟信号的频率，使用 修剪值。

    Demodulation of FM audio carrier
    10.
    发明授权
    Demodulation of FM audio carrier 失效
    FM音频载波解调

    公开(公告)号：US6160444A

    公开(公告)日：2000-12-12

    申请号：US840391

    申请日：1997-04-29

    Applicant: Wayne Leslie Horsfall ,  Gary Shipton

    Inventor： Wayne Leslie Horsfall ,  Gary Shipton

    IPC: H03L7/093 ,  H03D3/02 ,  H03D3/24 ,  H03D3/00 ,  H03L7/08

    CPC classification number: H03D3/244

    Abstract: A method of demodulating an FM carrier wave and an FM demodulation circuit are described which use a phase locked loop. The phase locked loop is tuned to a selected carrier wave frequency including the step of selecting a setting of the variable gain circuit in the phase locked loop to select desired loop gain.

    Abstract translation: 描述了使用锁相环的解调FM载波和FM解调电路的方法。 锁相环被调谐到选定的载波频率，包括在锁相环中选择可变增益电路的设置以选择期望的环路增益的步骤。

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