公开(公告)号：US07809886B2

公开(公告)日：2010-10-05

申请号：US12103987

申请日：2008-04-16

申请人： Paul Andrew Ashmore ,  Dwight Oliver Lintz ,  Gene Maine ,  Victor Key Pecone ,  Rex Weldon Vedder

发明人： Paul Andrew Ashmore ,  Dwight Oliver Lintz ,  Gene Maine ,  Victor Key Pecone ,  Rex Weldon Vedder

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F11/1441 ,  G06F1/3203 ,  G06F1/3268 ,  G06F12/0866 ,  Y02D10/154

摘要： A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

摘要翻译： 写缓存RAID控制器包括CPU，其管理从主计算机向易失性存储器的发布写入数据的传送，并且当主电源供应时将写入数据从易失性存储器传输到存储设备的冗余阵列 电源到RAID控制器。 存储器控制器将从主计算机接收到的贴写数据传送到易失性存储器，并将来自易失性存储器的发布写入数据传送到由CPU管理的存储设备的冗余阵列。 当主电源故障时，存储器控制器将写入数据从易失性存储器刷新到非易失性存储器，在此期间，电容器向存储器控制器，易失性存储器和非易失性存储器提供电力，而不向CPU提供电力， 以减少电容器的储能要求。 在主电源供电期间，CPU使用执行刷新操作所需的信息来对存储器控制器进行编程，例如易失性存储器中的写入 - 写入数据的位置和大小以及各种冲洗操作特性。

公开(公告)号：US07536506B2

公开(公告)日：2009-05-19

申请号：US11226825

申请日：2005-09-14

申请人： Paul Andrew Ashmore ,  Dwight Oliver Lintz ,  Gene Maine ,  Victor Key Pecone ,  Rex Weldon Vedder

发明人： Paul Andrew Ashmore ,  Dwight Oliver Lintz ,  Gene Maine ,  Victor Key Pecone ,  Rex Weldon Vedder

IPC分类号： G06F13/00 ,  G06F13/28

CPC分类号： G06F11/1441 ,  G06F1/3203 ,  G06F1/3268 ,  G06F12/0866 ,  Y02D10/154

摘要： A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

摘要翻译： 公开了一种写缓存RAID控制器。 控制器包括CPU，其管理从主计算机向易失性存储器的发布写入数据的传送，并且当主电源向RAID控制器供电时，将写入数据从易失性存储器传送到存储设备。 当主电源故障时，存储器控制器将易失性存储器中的贴写数据刷新到非易失性存储器，在此期间电容器向存储器控制器，易失性存储器和非易失性存储器提供电力，而不向CPU提供电力， 以减少电容器的储能要求。 在主电源供电期间，CPU使用执行刷新操作所需的信息来对存储器控制器进行编程，例如易失性存储器中的写入 - 写入数据的位置和大小以及各种冲洗操作特性。

公开(公告)号：US20060015683A1

公开(公告)日：2006-01-19

申请号：US11226825

申请日：2005-09-14

申请人： Paul Ashmore ,  Dwight Lintz ,  Gene Maine ,  Victor Pecone ,  Rex Vedder

发明人： Paul Ashmore ,  Dwight Lintz ,  Gene Maine ,  Victor Pecone ,  Rex Vedder

IPC分类号： G06F12/16

CPC分类号： G06F11/1441 ,  G06F1/3203 ,  G06F1/3268 ,  G06F12/0866 ,  Y02D10/154

摘要： A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

摘要翻译： 公开了一种写缓存RAID控制器。 控制器包括CPU，其管理从主计算机向易失性存储器的发布写入数据的传送，并且当主电源向RAID控制器供电时，将写入数据从易失性存储器传送到存储设备。 当主电源故障时，存储器控制器将易失性存储器中的贴写数据刷新到非易失性存储器，在此期间电容器向存储器控制器，易失性存储器和非易失性存储器提供电力，而不向CPU提供电力， 以减少电容器的储能要求。 在主电源供电期间，CPU使用执行刷新操作所需的信息来对存储器控制器进行编程，例如易失性存储器中的写入 - 写入数据的位置和大小以及各种冲洗操作特性。

公开(公告)号：US20080215808A1

公开(公告)日：2008-09-04

申请号：US12103987

申请日：2008-04-16

申请人： Paul Andrew Ashmore ,  Dwight Oliver Lintz ,  Gene Maine ,  Victor Key Pecone ,  Rex Weldon Vedder

发明人： Paul Andrew Ashmore ,  Dwight Oliver Lintz ,  Gene Maine ,  Victor Key Pecone ,  Rex Weldon Vedder

IPC分类号： G06F12/08

CPC分类号： G06F11/1441 ,  G06F1/3203 ,  G06F1/3268 ,  G06F12/0866 ,  Y02D10/154

摘要： A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.

摘要翻译： 写缓存RAID控制器包括CPU，其管理从主计算机向易失性存储器的发布写入数据的传送，并且当主电源供应时将写入数据从易失性存储器传输到存储设备的冗余阵列 电源到RAID控制器。 存储器控制器将从主计算机接收到的贴写数据传送到易失性存储器，并将来自易失性存储器的发布写入数据传送到由CPU管理的存储设备的冗余阵列。 当主电源故障时，存储器控制器将写入数据从易失性存储器刷新到非易失性存储器，在此期间电容器向存储器控制器，易失性存储器和非易失性存储器提供电力，而不向CPU提供电力， 以减少电容器的储能要求。 在主电源供电期间，CPU使用执行刷新操作所需的信息来对存储器控制器进行编程，例如易失性存储器中的写入 - 写入数据的位置和大小以及各种冲洗操作特性。

公开(公告)号：US20070088975A1

公开(公告)日：2007-04-19

申请号：US11253385

申请日：2005-10-18

申请人： Paul Ashmore ,  Gene Maine

发明人： Paul Ashmore ,  Gene Maine

IPC分类号： G06F11/00

CPC分类号： G06F11/2069 ,  G06F11/2066 ,  G06F11/2079

摘要： A data storage system configured for efficient mirroring of data between paired redundant controllers is provided. More particularly, in response to the receipt of customer data from a host for storage, a first controller segments the received customer data into one or more frames of data. In addition, the first controller determines or associates certain metadata for each frame of customer data, and inserts that metadata in the corresponding frame. The frames, including the metadata, are provided to a secondary controller. The secondary controller stores the customer data from a received frame in memory, and stores the corresponding metadata in another location of memory that is indexed to the location where the customer data was stored. The secondary controller may also associate a count value with each frame of data in order to distinguish the most recent frame of data should frames in memory have matching metadata.

摘要翻译： 提供了配置用于在配对的冗余控制器之间有效地镜像数据的数据存储系统。 更具体地，响应于从主机接收客户数据进行存储，第一控制器将所接收的客户数据分成一个或多个数据帧。 另外，第一控制器确定或关联客户数据的每一帧的某些元数据，并将该元数据插入相应的帧。 包括元数据的帧被提供给次级控制器。 次级控制器将来自接收到的帧的客户数据存储在存储器中，并将相应的元数据存储在索引到存储客户数据的位置的存储器的另一位置中。 次级控制器还可以将计数值与每个数据帧相关联，以便区分存储器中的帧的最新帧数据具有匹配的元数据。

公开(公告)号：US20060277347A1

公开(公告)日：2006-12-07

申请号：US11272340

申请日：2005-11-10

申请人： Paul Ashmore ,  Ian Davies ,  Gene Maine

发明人： Paul Ashmore ,  Ian Davies ,  Gene Maine

IPC分类号： G06F13/20

CPC分类号： G06F3/065 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0689 ,  G06F11/1666 ,  G06F11/2092 ,  G06F12/0866 ,  G06F2212/262 ,  G06F2212/286

摘要： A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.

摘要翻译： 主RAID控制器上的总线桥接器接收来自主机的用户写入数据，并将数据写入其高速缓存，并通过高速链路（例如，PCI-Express）将数据广播到辅助RAID控制器的总线桥上，该桥接器写入 数据到其镜像写缓存。 然而，在写入数据之前，第二总线桥自动使要写入数据的高速缓存缓冲区无效，这缓解了主控制器的CPU向辅助控制器的CPU发送消息以指示其使缓存缓冲区无效。 辅助控制器CPU在启动时使用其镜像写缓存的基地址对其总线桥进行编程，以使其能够检测到高速缓存缓冲区响应于广播写入而无效，并且其包含高速缓存的目录的基址 缓冲器有效位。

公开(公告)号：US6065102A

公开(公告)日：2000-05-16

申请号：US965718

申请日：1997-11-07

申请人： Michael J. Peters ,  Gene Maine

发明人： Michael J. Peters ,  Gene Maine

IPC分类号： G06F12/08 ,  G06F13/16 ,  G06F13/18

CPC分类号： G06F12/0866 ,  G06F13/1605 ,  G06F13/1694

摘要： A multiple client memory arbitration system supporting simultaneous arbitration access to a local cache memory and a remote cache memory for mirrored write operations to both the local cache memory and the remote cache memory by one of a local arbitration device or a remote cache memory at a time. The enhanced arbitration system includes active/active failover control by a surviving one of the local arbitration device or the remote arbitration device that have participated in the mirrored write operations between the respective local cache memory and the remote cache memory.

摘要翻译： 多个客户端存储器仲裁系统，一次支持本地高速缓冲存储器和远程高速缓冲存储器的同时仲裁访问到本地高速缓冲存储器和远程高速缓冲存储器，以用于本地高速缓冲存储器和远程高速缓冲存储器的镜像写入操作 。 增强的仲裁系统包括本地仲裁设备或参与在各自的本地高速缓冲存储器和远程高速缓冲存储器之间的镜像写入操作的远程仲裁设备中的幸存的一个的主动/主动故障切换控制。

公开(公告)号：US07380115B2

公开(公告)日：2008-05-27

申请号：US10484460

申请日：2002-11-07

申请人： Gene Maine

发明人： Gene Maine

IPC分类号： G06F12/08

CPC分类号： G06F13/28

摘要： A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes the DMA engine to access processor memory to obtain metadata therefrom. In performing a DMA operation, the metadata enables the DMA engine to conduct data transfers between local memory and remote memory. In performing exclusive OR operations, the DMA engine is involved with conducting data transfers using local memory.

摘要翻译： 直接存储器访问（DMA）引擎几乎与数据传输有关的所有控制可以涉及主控制器和辅助控制器之一或两者。 DMA引擎从与主控制器相关联的处理器接收与数据传输相关的命令。 该命令使得DMA引擎访问处理器存储器以从其获得元数据。 在执行DMA操作时，元数据允许DMA引擎在本地存储器和远程存储器之间进行数据传输。 在执行异或操作时，DMA引擎涉及使用本地存储进行数据传输。

公开(公告)号：US07340555B2

公开(公告)日：2008-03-04

申请号：US11272340

申请日：2005-11-10

申请人： Paul Andrew Ashmore ,  Ian Robert Davies ,  Gene Maine

发明人： Paul Andrew Ashmore ,  Ian Robert Davies ,  Gene Maine

IPC分类号： G06F13/20

CPC分类号： G06F3/065 ,  G06F3/0611 ,  G06F3/0617 ,  G06F3/0689 ,  G06F11/1666 ,  G06F11/2092 ,  G06F12/0866 ,  G06F2212/262 ,  G06F2212/286

摘要： A bus bridge on a primary RAID controller receives user write data from a host and writes the data to its write cache and also broadcasts the data over a high speed link (e.g., PCI-Express) to a secondary RAID controller's bus bridge, which writes the data to its mirroring write cache. However, before writing the data, the second bus bridge automatically invalidates the cache buffers to which the data is to be written, which alleviates the primary controller's CPU from sending a message to the secondary controller's CPU to instruct it to invalidate the cache buffers. The secondary controller CPU programs its bus bridge at boot time with the base address of its mirrored write cache to enable it to detect that the cache buffer needs invalidating in response to the broadcast write, and with the base address of its directory that includes the cache buffer valid bits.

摘要翻译： 主RAID控制器上的总线桥接器接收来自主机的用户写入数据，并将数据写入其高速缓存，并通过高速链路（例如，PCI-Express）将数据广播到辅助RAID控制器的总线桥上，该桥接器写入 数据到其镜像写缓存。 然而，在写入数据之前，第二总线桥自动使要写入数据的高速缓存缓冲区无效，这缓解了主控制器的CPU向辅助控制器的CPU发送消息以指示其使缓存缓冲区无效。 辅助控制器CPU在启动时使用其镜像写缓存的基地址对其总线桥进行编程，以使其能够检测到高速缓存缓冲区响应于广播写入而无效，并且其包含高速缓存的目录的基址 缓冲器有效位。

公开(公告)号：US07146448B2

公开(公告)日：2006-12-05

申请号：US10946341

申请日：2004-09-21

申请人： Ian Robert Davies ,  Gene Maine ,  Victor Key Pecone

发明人： Ian Robert Davies ,  Gene Maine ,  Victor Key Pecone

IPC分类号： G06F13/00

CPC分类号： G06F11/2092 ,  G06F11/2005 ,  G06F11/2033

摘要： A storage controller configured to adopt orphaned I/O ports is disclosed. The controller includes multiple field-replaceable units (FRUs) that plug into a backplane having local buses. At least two of the FRUs have microprocessors and memory for processing I/O requests received from host computers for accessing storage devices controlled by the controller. Other of the FRUs include I/O ports for receiving the requests from the hosts and bus bridges for bridging the I/O ports to the backplane local buses in such a manner that if one of the processing FRUs fails, the surviving processing FRU detects the failure and responsively adopts the I/O ports previously serviced by the failed FRU to service the subsequently received I/O requests on the adopted I/O ports. The I/O port FRUs also include I/O ports for transferring data with the storage devices that are also adopted by the surviving processing FRU.

摘要翻译： 公开了一种配置成采用孤立I / O端口的存储控制器。 控制器包括插入具有本地总线的背板的多个现场可更换单元（FRU）。 至少两个FRU具有微处理器和用于处理从主计算机接收的用于访问由控制器控制的存储设备的I / O请求的存储器。 其他FRU包括用于接收来自主机和总线桥的请求的I / O端口，用于将I / O端口桥接到背板本地总线，使得如果处理FRU中的一个FRU失败，则幸存处理FRU检测到 故障并且响应地采用先前由故障FRU服务的I / O端口来服务于在所采用的I / O端口上随后接收的I / O请求。 I / O端口FRU还包括用于与存活处理FRU所采用的存储设备传输数据的I / O端口。