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1.发明授权RAID controller using capacitor energy source to flush volatile cache data to non-volatile memory during main power outage 有权使用电容器能量的RAID控制器在主电源中断期间将易失性缓存数据刷新到非易失性存储器公开(公告)号：US07536506B2
公开(公告)日：2009-05-19
申请号：US11226825
申请日：2005-09-14
CPC分类号： G06F11/1441 , G06F1/3203 , G06F1/3268 , G06F12/0866 , Y02D10/154
摘要： A write-caching RAID controller is disclosed. The controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to storage devices when a main power source is supplying power to the RAID controller. A memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.
摘要翻译： 公开了一种写缓存RAID控制器。 控制器包括CPU，其管理从主计算机向易失性存储器的发布写入数据的传送，并且当主电源向RAID控制器供电时，将写入数据从易失性存储器传送到存储设备。 当主电源故障时，存储器控制器将易失性存储器中的贴写数据刷新到非易失性存储器，在此期间电容器向存储器控制器，易失性存储器和非易失性存储器提供电力，而不向CPU提供电力， 以减少电容器的储能要求。 在主电源供电期间，CPU使用执行刷新操作所需的信息来对存储器控制器进行编程，例如易失性存储器中的写入 - 写入数据的位置和大小以及各种冲洗操作特性。
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2.发明授权RAID controller using capacitor energy source to flush volatile cache data to non-volatile memory during main power outage 有权使用电容器能量的RAID控制器在主电源中断期间将易失性缓存数据刷新到非易失性存储器公开(公告)号：US07809886B2
公开(公告)日：2010-10-05
申请号：US12103987
申请日：2008-04-16
CPC分类号： G06F11/1441 , G06F1/3203 , G06F1/3268 , G06F12/0866 , Y02D10/154
摘要： A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.
摘要翻译： 写缓存RAID控制器包括CPU，其管理从主计算机向易失性存储器的发布写入数据的传送，并且当主电源供应时将写入数据从易失性存储器传输到存储设备的冗余阵列 电源到RAID控制器。 存储器控制器将从主计算机接收到的贴写数据传送到易失性存储器，并将来自易失性存储器的发布写入数据传送到由CPU管理的存储设备的冗余阵列。 当主电源故障时，存储器控制器将写入数据从易失性存储器刷新到非易失性存储器，在此期间，电容器向存储器控制器，易失性存储器和非易失性存储器提供电力，而不向CPU提供电力， 以减少电容器的储能要求。 在主电源供电期间，CPU使用执行刷新操作所需的信息来对存储器控制器进行编程，例如易失性存储器中的写入 - 写入数据的位置和大小以及各种冲洗操作特性。
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3.发明申请RAID CONTROLLER USING CAPACITOR ENERGY SOURCE TO FLUSH VOLATILE CACHE DATA TO NON-VOLATILE MEMORY DURING MAIN POWER OUTAGE 有权使用电容器能量源的RAID控制器在主电源输入期间将挥发性高速缓存数据闪存到非易失性存储器公开(公告)号：US20080215808A1
公开(公告)日：2008-09-04
申请号：US12103987
申请日：2008-04-16
IPC分类号： G06F12/08
CPC分类号： G06F11/1441 , G06F1/3203 , G06F1/3268 , G06F12/0866 , Y02D10/154
摘要： A write-caching RAID controller includes a CPU that manages transfers of posted-write data from host computers to a volatile memory and transfers of the posted-write data from the volatile memory to a redundant array of storage devices when a main power source is supplying power to the RAID controller. A memory controller transfers the posted-write data received from the host computers to the volatile memory and transfers the posted-write data from the volatile memory for transfer to the redundant array of storage devices as managed by the CPU. The memory controller flushes the posted-write data from the volatile memory to the non-volatile memory when main power fails, during which time capacitors provide power to the memory controller, volatile memory, and non-volatile memory, but not to the CPU, in order to reduce the energy storage requirements of the capacitors. During main power provision, the CPU programs the memory controller with information needed to perform the flush operation, such as the location and size of the posted-write data in the volatile memory and various flush operation characteristics.
摘要翻译： 写缓存RAID控制器包括CPU，其管理从主计算机向易失性存储器的发布写入数据的传送，并且当主电源供应时将写入数据从易失性存储器传输到存储设备的冗余阵列 电源到RAID控制器。 存储器控制器将从主计算机接收到的贴写数据传送到易失性存储器，并将来自易失性存储器的发布写入数据传送到由CPU管理的存储设备的冗余阵列。 当主电源故障时，存储器控制器将写入数据从易失性存储器刷新到非易失性存储器，在此期间电容器向存储器控制器，易失性存储器和非易失性存储器提供电力，而不向CPU提供电力， 以减少电容器的储能要求。 在主电源供电期间，CPU使用执行刷新操作所需的信息来对存储器控制器进行编程，例如易失性存储器中的写入 - 写入数据的位置和大小以及各种冲洗操作特性。
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4.发明授权Certified memory-to-memory data transfer between active-active raid controllers 有权在主动 - 主动式RAID控制器之间经过认证的内存到内存数据传输公开(公告)号：US07536495B2
公开(公告)日：2009-05-19
申请号：US11317504
申请日：2005-12-22
CPC分类号： G06F13/4269 , G06F11/2071 , G06F11/2074 , G06F11/2089
摘要： A system for performing an efficient mirrored posted-write operation having first and second RAID controllers in communication via a PCI-Express link is disclosed. The first bus bridge transmits a PCI-Express memory write request TLP to the second bus bridge. The TLP header includes an indication of whether the first CPU requests a certification that certifies the payload data has been written to the second write cache memory. If the indication requests the certification, the second bus bridge automatically transmits the certification to the first bus bridge independent of the second CPU, after writing the payload data to the second write cache memory. The first bus bridge generates an interrupt to the first CPU in response to receiving the certification. The certified transfer may be used to validate and/or invalidate mirrored copies of a write cache directory on the RAID controllers, among other uses.
摘要翻译： 公开了一种用于执行具有通过PCI-Express链路进行通信的第一和第二RAID控制器的有效镜像贴写操作的系统。 第一个总线桥将PCI-Express存储器写请求TLP发送到第二总线桥。 TLP报头包括第一CPU是否请求验证有效载荷数据已被写入第二写入高速缓冲存储器的指示。 如果指示请求认证，则在将有效载荷数据写入第二写入高速缓冲存储器之后，第二总线桥接器自动将认证发送到与第二CPU独立的第一总线桥。 第一个总线桥接器产生一个中断给第一个CPU，以响应接收认证。 认证的传输可用于验证和/或使RAID控制器上的写入缓存目录的镜像副本无效，以及其他用途。
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5.发明授权Method for efficient inter-processor communication in an active-active RAID system using PCI-express links 有权使用PCI-express链路的主动 - 主动式RAID系统中有效的处理器间通信的方法公开(公告)号：US07315911B2
公开(公告)日：2008-01-01
申请号：US11178727
申请日：2005-07-11
申请人： Ian Robert Davies , Gene Maine , Rex Weldon Vedder
发明人： Ian Robert Davies , Gene Maine , Rex Weldon Vedder
CPC分类号： G06F11/2089
摘要： A fault-tolerant RAID system is disclosed. The system includes redundant RAID controllers coupled by a PCI-Express link. When a PCI-Express controller of one of the RAID controllers receives a PCI-Express memory write request transaction layer packet (TLP), it interprets a predetermined bit in the header as an interrupt request flag, rather than as its standard function specified by the PCI-Express specification. If the flag is set, the PCI-Express controller interrupts the processor after storing the message in the payload at the specified memory location. In one embodiment, an unused upper address bit in the header is used as the interrupt request flag. Additionally, unused predetermined bits in the TLP header are used as a message tag to indicate one of a plurality of message buffers on the receiving RAID controller into which the message has been written. The PCI-Express controller sets a corresponding bit in a register to indicate which message buffer was written.
摘要翻译： 公开了容错RAID系统。 该系统包括通过PCI-Express链路耦合的冗余RAID控制器。 当其中一个RAID控制器的PCI-Express控制器接收到PCI-Express存储器写入请求事务层数据包（TLP）时，它会将头部中的预定位解释为中断请求标志，而不是作为其标准函数 PCI-Express规范。 如果标志置位，则PCI-Express控制器在将消息存储在指定内存位置的有效载荷中后中断处理器。 在一个实施例中，报头中的未使用的高位地址位用作中断请求标志。 此外，TLP报头中的未使用的预定比特被用作消息标签，以指示已经写入消息的接收RAID控制器上的多个消息缓冲区中的一个。 PCI-Express控制器在寄存器中设置相应的位，以指示写入哪个消息缓冲区。
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6.发明申请Buffer management method and apparatus for power reduction during flash operation 有权闪存操作期间功率降低的缓冲器管理方法和装置公开(公告)号：US20110239043A1
公开(公告)日：2011-09-29
申请号：US13012390
申请日：2011-01-24
CPC分类号： G06F1/263 , G06F1/3203 , G06F1/3275 , G11C5/141 , Y02D10/13 , Y02D10/14
摘要： A method for providing reduced power consumption in a computer memory system is provided. The method includes transferring, by a memory controller coupled to a volatile memory, a non-volatile memory, and a buffer, first data from the volatile memory to the buffer. The buffer stores less data than the volatile memory and the non-volatile memory. The method also includes placing the volatile memory into self-refresh mode after transferring the first data to the buffer. The method further includes conveying the first data from the buffer to the non-volatile memory, where the amount of first data exceeds a predetermined threshold. While conveying the first data, the memory controller takes the volatile memory out of self-refresh mode when the amount of first data in the buffer reaches the predetermined threshold. The volatile memory is ready to transfer second data to the buffer when the memory controller is finished transferring the first data.
摘要翻译： 提供了一种用于在计算机存储器系统中提供降低的功耗的方法。 该方法包括通过耦合到易失性存储器的存储器控制器将非易失性存储器和缓冲器从第一数据从易失性存储器传送到缓冲器。 缓冲器存储的数据少于易失性存储器和非易失性存储器。 该方法还包括在将第一数据传送到缓冲器之后将易失性存储器置于自刷新模式。 该方法还包括将第一数据从缓冲器传送到非易失性存储器，其中第一数据量超过预定阈值。 当传送第一数据时，当缓冲器中的第一数据量达到预定阈值时，存储器控制器将易失性存储器从自刷新模式中取出。 当存储器控制器完成传送第一个数据时，易失性存储器准备好将第二个数据传送到缓冲器。
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7.发明授权Memory calibration method and apparatus for power reduction during flash operation 有权闪存操作期间功率降低的存储器校准方法和设备公开(公告)号：US08694812B2
公开(公告)日：2014-04-08
申请号：US13012299
申请日：2011-01-24
IPC分类号： G06F1/00
CPC分类号： G06F1/263 , G06F1/3203 , G06F1/3275 , G11C5/141 , Y02D10/13 , Y02D10/14
摘要： A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.
摘要翻译： 提供了一种用于在计算机存储器系统中提供降低的功耗的方法。 该方法包括由处理器以第一和第二操作速度校准计算机存储器系统的易失性存储器，其中第二操作速度高于第一操作速度。 该方法还包括如果主电源向计算机存储器系统提供电力，则由连接到处理器和易失性存储器的存储器控制器以第二操作速度操作易失性存储器。 该方法还包括如果备用电源向存储器控制器和易失性存储器提供电力，则由存储器控制器以第一操作速度操作易失性存储器。 当计算机存储器系统的主电源丢失时，备用电源向存储器控制器和易失性存储器供电。
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8.发明授权Buffer management method and apparatus for power reduction during flush operation 有权冲洗运行期间功率降低的缓冲器管理方法和装置公开(公告)号：US08510598B2
公开(公告)日：2013-08-13
申请号：US13012390
申请日：2011-01-24
IPC分类号： G06F11/00
CPC分类号： G06F1/263 , G06F1/3203 , G06F1/3275 , G11C5/141 , Y02D10/13 , Y02D10/14
摘要： A method for providing reduced power consumption in a computer memory system is provided. The method includes transferring, by a memory controller coupled to a volatile memory, a non-volatile memory, and a buffer, first data from the volatile memory to the buffer. The buffer stores less data than the volatile memory and the non-volatile memory. The method also includes placing the volatile memory into self-refresh mode after transferring the first data to the buffer. The method further includes conveying the first data from the buffer to the non-volatile memory, where the amount of first data exceeds a predetermined threshold. While conveying the first data, the memory controller takes the volatile memory out of self-refresh mode when the amount of first data in the buffer reaches the predetermined threshold. The volatile memory is ready to transfer second data to the buffer when the memory controller is finished transferring the first data.
摘要翻译： 提供了一种用于在计算机存储器系统中提供降低的功耗的方法。 该方法包括通过耦合到易失性存储器的存储器控制器将非易失性存储器和缓冲器从第一数据从易失性存储器传送到缓冲器。 缓冲器存储的数据少于易失性存储器和非易失性存储器。 该方法还包括在将第一数据传送到缓冲器之后将易失性存储器置于自刷新模式。 该方法还包括将第一数据从缓冲器传送到非易失性存储器，其中第一数据量超过预定阈值。 当传送第一数据时，当缓冲器中的第一数据量达到预定阈值时，存储器控制器将易失性存储器从自刷新模式中取出。 当存储器控制器完成传送第一个数据时，易失性存储器准备好将第二个数据传送到缓冲器。
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9.发明申请Memory calibration method and apparatus for power reduction during flash operation 有权闪存操作期间功率降低的存储器校准方法和设备公开(公告)号：US20110239021A1
公开(公告)日：2011-09-29
申请号：US13012299
申请日：2011-01-24
IPC分类号： G06F1/32
CPC分类号： G06F1/263 , G06F1/3203 , G06F1/3275 , G11C5/141 , Y02D10/13 , Y02D10/14
摘要： A method for providing reduced power consumption in a computer memory system is provided. The method includes calibrating, by a processor, a volatile memory of the computer memory system at a first and a second operating speed, where the second operating speed is higher than the first operating speed. The method also includes operating, by a memory controller coupled to the processor and the volatile memory, the volatile memory at the second operating speed if a main power source provides power to the computer memory system. The method further includes operating, by the memory controller, the volatile memory at the first operating speed if a backup power source provides power to the memory controller and the volatile memory. The backup power source provides power to the memory controller and the volatile memory when there is a loss of main power to the computer memory system.
摘要翻译： 提供了一种用于在计算机存储器系统中提供降低的功耗的方法。 该方法包括由处理器以第一和第二操作速度校准计算机存储器系统的易失性存储器，其中第二操作速度高于第一操作速度。 该方法还包括如果主电源向计算机存储器系统提供电力，则由连接到处理器和易失性存储器的存储器控制器以第二操作速度操作易失性存储器。 该方法还包括如果备用电源向存储器控制器和易失性存储器提供电力，则由存储器控制器以第一操作速度操作易失性存储器。 当计算机存储器系统的主电源丢失时，备用电源向存储器控制器和易失性存储器供电。
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