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公开(公告)号：US5172396A
公开(公告)日：1992-12-15
申请号：US260184
申请日：1988-10-20
摘要： In a multiple site radio frequency simulcasting RF transmission system, data transmitted from a control point to the RF transmitter sites exhibits random time delay skew because multi-phase modems recover clock signals from an arbitrary one of the multiple phases. The outputs of the modems are temporarily stored at the sites by memory buffers. The control point derives resynchronization signals from a source data clock, this signal containing frequency and timing information. The resynchronization signal is distributed to the various sites via additional phase-stable, delay compensated channels. Each site is provided with a clock recovery circuit that recovers the original source data clocking signal from the resynchronization signal and also extracts read-out timing information from the resynchronization signal. The recovered data clocking signal and the readout timing information are used to synchronize the readout from the FIFO memory buffers--providing approximately simultaneous (coherent) readout of the same data bits from the respective buffers of the different simulcasting transmitter sites.
摘要翻译： 在多站点射频同播RF传输系统中，从控制点发送到RF发射机站点的数据表现出随机的时间延迟偏差，因为多相调制解调器从多个相位中的任一个恢复时钟信号。 调制解调器的输出由存储器缓冲器临时存储在站点处。 控制点从源数据时钟导出重新同步信号，该信号包含频率和定时信息。 再同步信号经由附加的相位稳定的延迟补偿信道分配给各个站点。 每个站点都设有一个时钟恢复电路，它从再同步信号恢复原始源数据时钟信号，并从再同步信号中提取读出定时信息。 恢复的数据时钟信号和读出定时信息用于使来自FIFO存储器缓冲器的读出同步 - 提供来自不同同播发射器站点的相应缓冲器的相同数据位的大致同时（相干）读出。
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公开(公告)号：US5517680A
公开(公告)日：1996-05-14
申请号：US824123
申请日：1992-01-22
摘要： Arrangements are disclosed for maintaining time synchronization of simulcast radio frequency communications system transmissions. A circuit continually instructs a modem to use the common system clocking signal, and modems are retrained whenever a channel is taken out of service because of a test call failure.
摘要翻译： 公开了用于维持联播射频通信系统传输的时间同步的安排。 电路连续地指示调制解调器使用公共系统时钟信号，并且每当通道由于测试呼叫失败而被取消服务时，调制解调器被重新训练。
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公开(公告)号：US5127101A
公开(公告)日：1992-06-30
申请号：US649049
申请日：1991-02-01
申请人： George D. Rose, Jr.
发明人： George D. Rose, Jr.
摘要： In a multisite radio frequency simulcasting transmission system involving microwave-multiplex distribution paths to several transmitting sites, each path including manually settable amplitude and time delay devices for equalization of the modulation in signal overlap areas among the various transmitter sites, an automatic simulcast alignment device is included in each distribution path whereby transmissions between a control point and each site transmitter are periodically tested and each path is compensated for amplitude and time delay variations to thus maintain equalized amplitude and time of arrival of the modulation in the transmitter site overlap areas. Thus, the instantaneous distribution of the FM modulation sidebands is maintained to be ideally identical in the signal overlap areas.
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公开(公告)号：US4388703A
公开(公告)日：1983-06-14
申请号：US181423
申请日：1980-08-26
IPC分类号： G11C17/06 , G11C17/16 , H01L23/525 , H01L27/02 , H03K19/091 , G11C11/40
CPC分类号： H01L23/5256 , G11C17/16 , H01L27/0244 , H03K19/091 , H01L2924/0002 , H01L2924/3011
摘要： A memory device is provided for an integrated injection logic (I.sup.2 L) device in solid state form by a resistor connected at one end to the logic device, and a diode having its cathode connected to the other end of the resistor at a programming junction, and its anode connected to a common point. If the diode conductors are melted or deformed by reverse diode current from the programming junction to the common point, a low impedance path is formed, and the logic portion is provided with a first logic input. If the diode conductors are left unmelted or intact, the logic portion is provided with a second logic input.
摘要翻译： 通过在一端连接到逻辑器件的电阻器以及在阴极连接到编程接点处的电阻器另一端的二极管，以固态形式提供集成注入逻辑（I2L）器件的存储器件，以及 其阳极连接到公共点。 如果二极管导体由编程结到公共点的反向二极管电流熔化或变形，则形成低阻抗路径，逻辑部分提供第一逻辑输入。 如果二极管导体未熔化或完整，则逻辑部分设置有第二逻辑输入。
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