Automated test generation for structural coverage for temporal logic falsification of cyber-physical systems

    公开(公告)号:US10409706B2

    公开(公告)日:2019-09-10

    申请号:US15721243

    申请日:2017-09-29

    Abstract: One embodiment is a methodology for model verification. An embodiment obtaining, by a processor, a model for a system; identifying, by the processor, at least one block within the model that has a branching structure; identifying, by the processor, at least one model variable affecting a switching condition of the identified at least one block; generating, by the processor, an extended finite state machine modeling a switching behavior of the identified at least one block by using the at least one model variable; combining, by the processor, at least one output variable of the extended finite state machine with at least one of a first output port and a second output port of the system included in the model; and performing, by the processor, model verification and coverage of the model that utilizes outputs from the first output port and the second output port to verify the model.

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