公开(公告)号：US06313660B1

公开(公告)日：2001-11-06

申请号：US09419921

申请日：1999-10-18

申请人： Gerald Edward Sobelman ,  David Parker

发明人： Gerald Edward Sobelman ,  David Parker

IPC分类号： G06F738

CPC分类号： H03K19/1735

摘要： A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

摘要翻译： 公开了一种用于实现异步逻辑的可编程门阵列。 在一个实施例中，阵列包括一组单元，其中至少一个包括具有多个输入，输出和阈值的阈值门。 信号可以假设具有逻辑含义的ASSERTED状态和没有逻辑含义的NULL状态。 当所有输入为NULL时，门输出切换到NULL，当ASSERTED输入的数量超过阈值时，切换到ASSERTED状态。 在优选实施例中，门显示滞后，使得输出保持为ASSERTED，而ASSERTED输入的数量保持大于零，小于阈值。 在替代实施例中，使用简化阈值元素的阵列来形成更复杂的阈值门。

公开(公告)号：US06020754A

公开(公告)日：2000-02-01

申请号：US50375

申请日：1998-03-31

申请人： Gerald Edward Sobelman ,  David Parker ,  Karl M. Fant

发明人： Gerald Edward Sobelman ,  David Parker ,  Karl M. Fant

IPC分类号： G06F7/50 ,  G06F7/505 ,  G06F11/08 ,  H03K19/08 ,  H03K19/096 ,  H03K19/23 ,  H03M5/02 ,  H03M5/16

CPC分类号： G06F7/5052 ,  G06F11/085 ,  G06F7/502 ,  H03K19/0813 ,  H03K19/096 ,  H03K19/23 ,  H03M5/02 ,  H03M5/16 ,  G06F2207/4822

摘要： A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume a DATA state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of DATA inputs exceeds the threshold value. The gate preferably exhibit hysteresis such that the output remains DATA while the number of DATA inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, and array of simplified threshold elements is used to form more complex threshold gates.

摘要翻译： 公开了一种用于实现异步逻辑的可编程门阵列。 在一个实施例中，阵列包括一组单元，其中的至少一个被编程为用作具有多个输入，输出和阈值的阈值门。 信号可以假设具有逻辑含义的DATA状态和没有逻辑含义的NULL状态。 当所有输入为NULL时，门输出切换到NULL，当DATA输入的数量超过阈值时，切换到ASSERTED状态。 门优选地显示滞后，使得输出保持DATA，而DATA输入的数量保持大于零并小于阈值。 在替代实施例中，使用简化阈值元素阵列来形成更复杂的阈值门。

公开(公告)号：US5986466A

公开(公告)日：1999-11-16

申请号：US947165

申请日：1997-10-08

申请人： Gerald Edward Sobelman ,  David Parker

发明人： Gerald Edward Sobelman ,  David Parker

IPC分类号： H03K19/173 ,  H03K19/177

CPC分类号： H03K19/1735

摘要： A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

摘要翻译： 公开了一种用于实现异步逻辑的可编程门阵列。 在一个实施例中，阵列包括一组单元，其中至少一个包括具有多个输入，输出和阈值的阈值门。 信号可以假设具有逻辑含义的ASSERTED状态和没有逻辑含义的NULL状态。 当所有输入为NULL时，门输出切换到NULL，当ASSERTED输入的数量超过阈值时，切换到ASSERTED状态。 在优选实施例中，门显示滞后，使得输出保持为ASSERTED，而ASSERTED输入的数量保持大于零且小于阈值。 在替代实施例中，使用简化阈值元素的阵列来形成更复杂的阈值门。

公开(公告)号：US06262593B1

公开(公告)日：2001-07-17

申请号：US09004335

申请日：1998-01-08

申请人： Gerald Edward Sobelman ,  Jason J. Hinze

发明人： Gerald Edward Sobelman ,  Jason J. Hinze

IPC分类号： H03K1923

CPC分类号： H03K19/0813

摘要： An m-of-n threshold gate is disclosed having an output stated derived from the voltage of a signal node. A “Go-to-Data” circuit pulls the signal node to a first state, corresponding to an ASSERTED (logically meaningful) output when a threshold number of inputs is in the ASSERTED state. A “Go-to-NULL” circuit pulls the signal node to a second state, corresponding to a NULL (logically meaningless) output when all inputs are in the NULL state. In a semi-dynamic embodiment, a weak feedback transistor holds the signal node in a predetermined state when some, but less than the threshold number of inputs is ASSERTED. In a dynamic embodiment, the signal node becomes isolated when less than the threshold number of inputs is ASSERTED, but holds sufficient charge to maintain the signal node in a state that existed at the time of isolation. A variety of GTN circuits are disclosed. Gates can be modified for the NULL state to be represented as ground (non-inverted) or other reference voltage (inverted). Alternating stages of inverted and non-inverted circuits can be used.

摘要翻译： 公开了一个n阈值门限，其具有从信号节点的电压导出的输出。 当阈值数量的输入处于ASSERTED状态时，“Go-to-Data”电路将信号节点拉到第一状态，对应于ASSERTED（逻辑上有意义的）输出。 当所有输入处于NULL状态时，“到空”电路将信号节点拉至第二状态，对应于NULL（逻辑上无意义的）输出。 在半动态实施例中，弱反馈晶体管将信号节点保持在预定状态，当一些但小于阈值数量的输入被确认时。 在动态实施例中，当小于阈值数量的输入被估计时，信号节点变得隔离，但是保持足够的电荷以将信号节点保持在隔离时存在的状态。 公开了各种GTN电路。 门可以修改为空状态表示为接地（非反相）或其他参考电压（反相）。 可以使用反相和非反相电路的交替级。

公开(公告)号：US6043674A

公开(公告)日：2000-03-28

申请号：US4336

申请日：1998-01-08

申请人： Gerald Edward Sobelman

发明人： Gerald Edward Sobelman

IPC分类号： H03K19/08 ,  H03K19/23 ,  H03K19/01 ,  H03K19/096

CPC分类号： H03K19/23 ,  H03K19/0813

摘要： Threshold logic gates are disclosed that respond to signals that may assume at least a first state having an arithmetic or logic meaning, and a second NULL state that has no arithmetic or logic meaning. Threshold values may be equal to or less than the number of input signal lines. Threshold gates switch their outputs from NULL to a meaningful state when the threshold number of inputs assume meaningful states. Gates will hold outputs in a meaningful (or non-null) state when the number of asserted inputs remains positive, even if the number is less than the threshold. In one embodiment, threshold gates include a "FLASH" input that forces the gate to NULL. In another embodiment, threshold gates include one or more "SET" inputs that drive the gate output to NULL or to a meaningfull state.

摘要翻译： 公开了阈值逻辑门，其对可能呈现具有算术或逻辑含义的至少第一状态的信号以及不具有算术或逻辑含义的第二NULL状态进行响应。 阈值可以等于或小于输入信号线的数量。 阈值门将输出从NULL切换到有意义的状态，当阈值输入数假定有意义状态时。 即使数字小于阈值，当有效输入的数量保持为正时，门将保持有意义（或非空）状态的输出。 在一个实施例中，阈值门包括强制门为NULL的“FLASH”输入。 在另一个实施例中，阈值门包括一个或多个将门输出驱动为NULL或意义的状态的“SET”输入。