公开(公告)号：US07298160B2

公开(公告)日：2007-11-20

申请号：US10784784

申请日：2004-02-24

申请人： Gi-Young Yang ,  Yong-Un Jang

发明人： Gi-Young Yang ,  Yong-Un Jang

IPC分类号： G01R31/26 ,  G01R27/26

CPC分类号： G01R31/2639

摘要： A gate capacitance of a MOS transistor is determined by (a) measuring the gate capacitance and dissipation factor; (b) obtaining a channel resistance and a tunneling resistance; (c) setting an initial capacitance and an error dissipation factor; (d) calculating a direct dissipation factor using the channel resistance, the tunneling resistance, and the initial capacitance; (e) calculating a calculated dissipation factor using the error dissipation factor, the direct dissipation factor, and the measured dissipation factor; (f) calculating a calculated capacitance using the channel resistance, the tunneling resistance, the initial capacitance, the error dissipation factor, and the measured dissipation factor; and (g) detecting the initial capacitance as an accurate gate capacitance of the transistor if it is determined that the calculated capacitance is equal to the measured capacitance and the calculated dissipation factor is equal to the measured dissipation factor, and otherwise repeating steps (c) through (g).

摘要翻译： MOS晶体管的栅极电容由（a）测量栅极电容和损耗因子确定; （b）获得通道阻力和隧道阻力; （c）设置初始电容和误差因子; （d）使用沟道电阻，隧穿电阻和初始电容计算直接耗散因数; （e）使用误差耗散因子，直接耗散因子和测量的耗散因数计算计算的耗散因数; （f）使用沟道电阻，隧道电阻，初始电容，误差耗散因数和测量的耗散因数计算计算电容; 如果确定计算出的电容值等于被测量的电容，并且所计算的耗散因数等于测量的耗散因数，则（g）检测初始电容为晶体管的精确栅极电容，否则重复步骤（c） 通过（g）。

公开(公告)号：US07405090B2

公开(公告)日：2008-07-29

申请号：US11638001

申请日：2006-12-13

申请人： Yong-Un Jang

发明人： Yong-Un Jang

IPC分类号： G01R31/26 ,  H01L21/66 ,  H01L21/336

CPC分类号： H01L22/14

摘要： In a method of measuring an effective channel length and an overlap length, first to third metal-oxide semiconductor field effect transistors (MOSFETs) including first to third gate patterns, respectively, are formed on a substrate. A parasitic capacitance between the gate patterns and the substrate in the MOSFETs is determined based on first and second capacitances, which are measured by applying a first voltage between the gate patterns and the substrate. A second voltage is applied between the first gate pattern and the substrate in the first MOSFET and a third voltage between the third gate pattern and the substrate in the third MOSFET to measure capacitances. The capacitances are treated to obtain third and fourth capacitances excluding the parasitic capacitance. Overlap lengths of the gate patterns are obtained based on the third and fourth capacitances. Effective channel lengths of the gate patterns are obtained based on the overlap length.

摘要翻译： 在测量有效沟道长度和重叠长度的方法中，分别在衬底上形成包括第一至第三栅极图案的第一至第三金属氧化物半导体场效应晶体管（MOSFET）。 基于通过在栅极图案和衬底之间施加第一电压来测量的第一和第二电容来确定MOSFET中的栅极图案和衬底之间的寄生电容。 在第一MOSFET中的第一栅极图案和衬底之间施加第二电压，并且在第三MOSFET中的第三栅极图案和衬底之间施加第三电压以测量电容。 处理电容以获得不包括寄生电容的第三和第四电容。 基于第三和第四电容获得栅极图案的重叠长度。 基于重叠长度获得栅极图案的有效沟道长度。

公开(公告)号：US20070161194A1

公开(公告)日：2007-07-12

申请号：US11638001

申请日：2006-12-13

申请人： Yong-Un Jang

发明人： Yong-Un Jang

IPC分类号： H01L21/336

CPC分类号： H01L22/14

摘要： In a method of measuring an effective channel length and an overlap length, first to third metal-oxide semiconductor field effect transistors (MOSFETs) including first to third gate patterns, respectively, are formed on a substrate. A parasitic capacitance between the gate patterns and the substrate in the MOSFETs is determined based on first and second capacitances, which are measured by applying a first voltage between the gate patterns and the substrate. A second voltage is applied between the first gate pattern and the substrate in the first MOSFET and a third voltage between the third gate pattern and the substrate in the third MOSFET to measure capacitances. The capacitances are treated to obtain third and fourth capacitances excluding the parasitic capacitance. Overlap lengths of the gate patterns are obtained based on the third and fourth capacitances. Effective channel lengths of the gate patterns are obtained based on the overlap length.

摘要翻译： 在测量有效沟道长度和重叠长度的方法中，分别在衬底上形成包括第一至第三栅极图案的第一至第三金属氧化物半导体场效应晶体管（MOSFET）。 基于通过在栅极图案和衬底之间施加第一电压来测量的第一和第二电容来确定MOSFET中的栅极图案和衬底之间的寄生电容。 在第一MOSFET中的第一栅极图案和衬底之间施加第二电压，并且在第三MOSFET中的第三栅极图案和衬底之间施加第三电压以测量电容。 处理电容以获得不包括寄生电容的第三和第四电容。 基于第三和第四电容获得栅极图案的重叠长度。 基于重叠长度获得栅极图案的有效沟道长度。