公开(公告)号：US09958493B2

公开(公告)日：2018-05-01

申请号：US15309584

申请日：2015-03-16

申请人： SHIN-ETSU HANDOTAI CO., LTD.

发明人： Takashi Aratani

IPC分类号： G01R31/02 ,  G01R31/26 ,  C30B29/06 ,  C30B33/00 ,  C30B15/20 ,  C30B15/30

CPC分类号： G01R31/2639 ,  C30B15/20 ,  C30B15/30 ,  C30B29/06 ,  C30B33/00 ,  C30B33/005 ,  C30B33/02 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20

摘要： A method evaluates a defect region of a semiconductor substrate based on C-V characteristics of a MOS structure formed on the semiconductor substrate, including determining a relationship between defect region and flat band voltage or fixed charge density by using a semiconductor substrate having a known defect region, under a heat treatment condition and a C-V characteristic evaluating condition identical to conditions for evaluating a defect region of a semiconductor substrate to be evaluated, determining a flat band voltage or a fixed charge density of the semiconductor substrate to be evaluated from C-V characteristics of a MOS structure formed on the semiconductor substrate to be evaluated, and identifying the defect region of the semiconductor substrate to be evaluated based on the relationship between defect region and flat band voltage or fixed charge density previously determined, whereby the defect region of the semiconductor substrate is evaluated.

公开(公告)号：US20170160335A1

公开(公告)日：2017-06-08

申请号：US15309584

申请日：2015-03-16

申请人： SHIN-ETSU HANDOTAI CO., LTD.

发明人： Takashi ARATANI

IPC分类号： G01R31/26 ,  C30B29/06

CPC分类号： G01R31/2639 ,  C30B15/20 ,  C30B15/30 ,  C30B29/06 ,  C30B33/00 ,  C30B33/005 ,  C30B33/02 ,  H01L22/12 ,  H01L22/14 ,  H01L22/20

摘要： A method evaluates a defect region of a semiconductor substrate based on C-V characteristics of a MOS structure formed on the semiconductor substrate, including determining a relationship between defect region and flat band voltage or fixed charge density by using a semiconductor substrate having a known defect region, under a heat treatment condition and a C-V characteristic evaluating condition identical to conditions for evaluating a defect region of a semiconductor substrate to be evaluated, determining a flat band voltage or a fixed charge density of the semiconductor substrate to be evaluated from C-V characteristics of a MOS structure formed on the semiconductor substrate to be evaluated, and identifying the defect region of the semiconductor substrate to be evaluated based on the relationship between defect region and flat band voltage or fixed charge density previously determined, whereby the defect region of the semiconductor substrate is evaluated.

公开(公告)号：US09429598B2

公开(公告)日：2016-08-30

申请号：US14320143

申请日：2014-06-30

申请人： Infineon Technologies AG

发明人： Rainald Sander

IPC分类号： G01R19/00 ,  G01R31/26

CPC分类号： G01R19/0092 ,  G01R31/2607 ,  G01R31/2639

摘要： A semiconductor arrangement may include a multiplicity of semiconductor elements with controlling paths and controlled paths, the controlled paths having controllable conductivities and being connected parallel to each other. The semiconductor arrangement may also include a current evaluation circuit configured to measure current strengths of currents present in the controlled paths and to provide a signal representing the sum of the measured current strengths, and a control circuit connected to the controlling paths and configured to control the conductivities of the controlled paths in accordance with an input signal and the signal representing the sum of the current strengths. The at least one controlled path is controlled to have minimum conductivity if the signal representing the sum of the current strengths is below a threshold value.

摘要翻译： 半导体布置可以包括具有控制路径和受控路径的多个半导体元件，所述受控路径具有可控制的导电性并且彼此并联连接。 半导体布置还可以包括电流评估电路，其被配置为测量存在于受控路径中的电流的电流强度，并且提供表示所测量的电流强度之和的信号，以及连接到控制路径并被配置为控制 根据输入信号的受控路径的电导率和表示当前强度之和的信号。 如果表示电流强度之和的信号低于阈值，则至少一个受控路径被控制为具有最小的导电性。

公开(公告)号：US20090206865A1

公开(公告)日：2009-08-20

申请号：US12212289

申请日：2008-09-17

申请人： Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

发明人： Lisa V. Rozario ,  Andy Strachan ,  Richard Orr

IPC分类号： G01R31/26 ,  H01L23/58

CPC分类号： G01R31/2623 ,  G01R31/2639 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test structure and testing method are provided for characterizing the time-dependent drift in the parasitic PFET leakage current that flows along the sidewall of a deep trench isolation structure from the P-type active area to the P-type substrate in a semiconductor integrated circuit structure. The capacitive coupling characteristics of the deep trench isolation structure are used to control the electrical “bias” of the deep trench structure through the use of a large auxiliary trench mesh network that is formed as part of the deep trench structure. The trench mesh network can be placed adjacent to a Vdd ring or a ground ring and then, by using a ratioed capacitive voltage dividing network, the electrical potential at the trench can be controlled.

摘要翻译： 提供了一种测试结构和测试方法，用于表征在半导体集成电路中沿着深沟槽隔离结构的侧壁从P型有源区流向P型衬底的寄生PFET漏电流中的时间依赖性漂移 结构体。 深沟槽隔离结构的电容耦合特性用于通过使用形成为深沟槽结构的一部分的大的辅助沟槽网状网来控制深沟槽结构的电“偏置”。 沟槽网状网络可以靠近Vdd环或接地环放置，然后通过使用比例的电容分压网络，可以控制沟槽处的电位。

公开(公告)号：US07298160B2

公开(公告)日：2007-11-20

申请号：US10784784

申请日：2004-02-24

申请人： Gi-Young Yang ,  Yong-Un Jang

发明人： Gi-Young Yang ,  Yong-Un Jang

IPC分类号： G01R31/26 ,  G01R27/26

CPC分类号： G01R31/2639

摘要： A gate capacitance of a MOS transistor is determined by (a) measuring the gate capacitance and dissipation factor; (b) obtaining a channel resistance and a tunneling resistance; (c) setting an initial capacitance and an error dissipation factor; (d) calculating a direct dissipation factor using the channel resistance, the tunneling resistance, and the initial capacitance; (e) calculating a calculated dissipation factor using the error dissipation factor, the direct dissipation factor, and the measured dissipation factor; (f) calculating a calculated capacitance using the channel resistance, the tunneling resistance, the initial capacitance, the error dissipation factor, and the measured dissipation factor; and (g) detecting the initial capacitance as an accurate gate capacitance of the transistor if it is determined that the calculated capacitance is equal to the measured capacitance and the calculated dissipation factor is equal to the measured dissipation factor, and otherwise repeating steps (c) through (g).

摘要翻译： MOS晶体管的栅极电容由（a）测量栅极电容和损耗因子确定; （b）获得通道阻力和隧道阻力; （c）设置初始电容和误差因子; （d）使用沟道电阻，隧穿电阻和初始电容计算直接耗散因数; （e）使用误差耗散因子，直接耗散因子和测量的耗散因数计算计算的耗散因数; （f）使用沟道电阻，隧道电阻，初始电容，误差耗散因数和测量的耗散因数计算计算电容; 如果确定计算出的电容值等于被测量的电容，并且所计算的耗散因数等于测量的耗散因数，则（g）检测初始电容为晶体管的精确栅极电容，否则重复步骤（c） 通过（g）。

公开(公告)号：US4325025A

公开(公告)日：1982-04-13

申请号：US152226

申请日：1980-05-22

申请人： Richard A. Corcoran ,  William A. Keenan ,  Demetrios Michaelides ,  Bob H. Yun

发明人： Richard A. Corcoran ,  William A. Keenan ,  Demetrios Michaelides ,  Bob H. Yun

IPC分类号： G01N27/00 ,  G01N27/04 ,  G01R31/26 ,  H01L21/66 ,  G01R27/26

CPC分类号： G01R31/2639

摘要： An apparatus for measuring the surface potential and impurity concentration in a semi-conductor body by monitoring the current flowing in a semiconductor body when the body is biased with a ramp voltage above its flat band voltage and summing the monitored current with the ramp voltage biasing the body. The apparatus provides direct measurement of surface potential and impurity concentration in a semiconductor structure and is especially useful in metal insulator semiconductor (MIS) structures.

摘要翻译： 一种用于通过监测半导体本体中流动的电流来测量半导体体中的表面电位和杂质浓度的装置，当体被斜坡电压高于其平带电压并且将所监视的电流与斜坡电压相加时 身体。 该装置提供对半导体结构中的表面电位和杂质浓度的直接测量，并且在金属绝缘体半导体（MIS）结构中特别有用。

公开(公告)号：US4323842A

公开(公告)日：1982-04-06

申请号：US122208

申请日：1980-02-19

申请人： James M. McGarrity ,  Harold E. Boesch, Jr.

发明人： James M. McGarrity ,  Harold E. Boesch, Jr.

IPC分类号： G01R31/26 ,  G01R31/265

CPC分类号： G01R31/265 ,  G01R31/2639

摘要： A method and apparatus are disclosed for testing susceptibility of a gate insulator in MOS and MIS devices to irradiation without use of ionizing radiation. The method consists of simulating the effects of radiation by applying a high magnitude, pulsed electric field to the device under test. An apparatus capable of determining the relationship between voltage applied to the device under test and the device capacitance is used to provide the desired susceptibility information.

摘要翻译： 公开了一种用于测试MOS和MIS器件中的栅极绝缘体对不使用电离辐射的照射的敏感性的方法和装置。 该方法包括通过对被测器件施加大幅度的脉冲电场来模拟辐射的影响。 使用能够确定施加到被测器件的电压与器件电容之间的关系的器件来提供期望的敏感性信息。

公开(公告)号：US20180188316A1

公开(公告)日：2018-07-05

申请号：US15910766

申请日：2018-03-02

申请人： Fifth Electronics Research Institute of Ministry of Industry and Information Technology

发明人： Yiqiang Chen ,  Yunfei En ,  Xiaowen Zhang ,  Yun Huang ,  Yudong Lu

IPC分类号： G01R31/26 ,  G01R31/28

CPC分类号： G01R31/2642 ,  G01R31/2601 ,  G01R31/2639 ,  G01R31/2858

摘要： A method for predicting remaining life of electromigration failure is disclosed. The methods includes: establishing an electromigration life model of a MOS device; acquiring a normal electromigration failure lifetime τ1, based on a current density and a first environment temperature under a preset normal operating condition and the electromigration life model; acquiring a current density stress, based on a target prognostic point τ2, a second environment temperature and the electromigration life model; inputting the current density stress into a MOS device electromigration failure warning circuit based on a prognostic cell; and if the prognostic circuit of EM failure for a MOS device outputs a high level after a time τ3, acquiring a remaining life of electromigration failure corresponding to τ2′ based on τ1, τ2 and τ3. A device for remaining life prediction for electromigration failure is also disclosed.

公开(公告)号：US20170356952A1

公开(公告)日：2017-12-14

申请号：US15178650

申请日：2016-06-10

申请人： Integrated Device Technology, Inc.

发明人： Pak-Kim Lau

IPC分类号： G01R31/26 ,  H01L49/02 ,  H01L21/66 ,  G01R27/26

CPC分类号： G01R31/2639 ,  G01R27/2605 ,  H01L22/14 ,  H01L28/20

摘要： An apparatus includes a resistor and a circuit. The resistor may be fabricated on a die using a semiconductor process. The circuit may be fabricated on the die using the semiconductor process and may be configured to (i) generate a measurement voltage at a node of the resistor as a function of a capacitance value and a frequency of a clock signal and (ii) generate a codeword in response to the measurement voltage. The codeword generally has a plurality of possible values. A particular value of the possible values may verify that the voltage is between a plurality of threshold voltages.

公开(公告)号：US09702919B2

公开(公告)日：2017-07-11

申请号：US15125332

申请日：2014-12-24

申请人： JOLED INC.

发明人： Mario Amatsuchi

IPC分类号： G01R31/02 ,  G01M11/02 ,  G01R31/26 ,  G09G3/20

CPC分类号： G01R31/022 ,  G01M11/0257 ,  G01M11/0264 ,  G01R31/02 ,  G01R31/26 ,  G01R31/2635 ,  G01R31/2639 ,  G01R31/44 ,  G09G3/006 ,  G09G3/2003 ,  G09G3/3233 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2310/0256 ,  G09G2310/0262 ,  G09G2320/0233 ,  G09G2330/10

摘要： A method for manufacturing a display panel including a display unit in which pixels, in rows and columns, include an organic EL element and a drive transistor, includes, performed on the display panel having a line defect which is a pixel column that emits light of luminance not reflecting display gray level signals: displaying, overlappingly, a lighted line, which is a pixel column inputted with uniform display gray level signals, and the line defect by displaying the lighted line on the display unit and scanning the display unit with the lighted line in the row direction; reducing a bright/dark part range in the line defect by uniformly changing the display gray level inputted to the pixel column in the lighted line overlapping with the line defect; and identifying a defective pixel, which is the line defect origin, from the position of the reduced bright/dark part range in the display unit.