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公开(公告)号：US07930689B2
公开(公告)日：2011-04-19
申请号：US11186271
申请日：2005-07-21
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译： 提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。 在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。 软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。 其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件， 其中所述存储器元件未映射到所述处理器的数据存储器空间。
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公开(公告)号：US07533250B2
公开(公告)日：2009-05-12
申请号：US11188311
申请日：2005-07-25
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor comprising a decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, where the single instruction requires an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit, modifies the operand, and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译： 一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。 处理器还包括耦合到解码逻辑的第二存储单元。 解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则处理一组指令来代替单个指令，其中单个指令需要操作数。 如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，修改操作数，并将操作数存储到第二存储单元以供指令组使用。
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公开(公告)号：US20060026412A1
公开(公告)日：2006-02-02
申请号：US11186036
申请日：2005-07-21
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device that comprises a processor including an individual instruction and a first group of instructions. The device further comprises a memory externally coupled to the processor, as well as a second group of instructions. When executed, the first group of instructions causes the processor to execute the second group of instructions in lieu of the individual instruction.
摘要翻译： 一种电子设备，包括包括单独指令和第一组指令的处理器。 该设备还包括外部耦合到处理器的存储器以及第二组指令。 当执行时，第一组指令使得处理器执行第二组指令来代替单独的指令。
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公开(公告)号：US20060026398A1
公开(公告)日：2006-02-02
申请号：US11116918
申请日：2005-04-28
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes an instruction that causes a source data field from a programmable position within a first source register to be copied to a destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译： 处理器执行使来自第一源寄存器中的可编程位置的源数据字段被复制到目的地寄存器的指令。 该指令对于生成基于媒体的比特流（例如，音频，视频）特别有用。 在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。
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公开(公告)号：US20060026391A1
公开(公告)日：2006-02-02
申请号：US11188827
申请日：2005-07-25
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： A processor that comprises decode logic coupled to a first storage unit and comprising a data structure. The processor also comprises a second storage unit coupled to the decode logic. The decode logic obtains a single instruction from the first storage unit and, if indicated by a first bit in the data structure, processes a group of instructions in lieu of the single instruction, the single instruction requiring an operand. If indicated by a second bit in the data structure, the decode logic obtains the operand from the first storage unit and stores the operand to the second storage unit for use by the group of instructions.
摘要翻译： 一种处理器，包括耦合到第一存储单元并包括数据结构的解码逻辑。 处理器还包括耦合到解码逻辑的第二存储单元。 解码逻辑从第一存储单元获得单个指令，并且如果由数据结构中的第一位指示，则代替单个指令处理一组指令，需要操作数的单个指令。 如果由数据结构中的第二位指示，则解码逻辑从第一存储单元获得操作数，并将操作数存储到第二存储单元以供指令组使用。
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公开(公告)号：US20060026370A1
公开(公告)日：2006-02-02
申请号：US11186271
申请日：2005-07-21
IPC分类号： G06F12/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： Systems, methods, and storage media for accessing indirect memory in Java applications are provided. In some embodiments, a storage medium is provided that comprises Java application software that performs one or more operations on an indirect memory of a device. The software comprises instructions that create an instance of a Java class representing the indirect memory, and instructions that access a memory element of the indirect memory using an element unique identifier (“euid”) of the memory element. Other embodiments provide a method for accessing memory elements of a device that comprises creating an instance of a Java class representing the memory elements, and accessing a memory element of the memory elements using an element unique identifier (“euid”) of the memory element, wherein the memory elements are not mapped into the data memory space of the processor.
摘要翻译： 提供了用于在Java应用程序中访问间接内存的系统，方法和存储介质。 在一些实施例中，提供存储介质，其包括在设备的间接存储器上执行一个或多个操作的Java应用软件。 软件包括创建表示间接存储器的Java类的实例的指令以及使用存储器元件的元素唯一标识符（“euid”）访问间接存储器的存储器元件的指令。 其他实施例提供了一种用于访问设备的存储器元件的方法，包括创建表示存储器元件的Java类的实例，以及使用存储元件的元素唯一标识符（“euid”）访问存储器元件的存储器元件， 其中所述存储器元件未映射到所述处理器的数据存储器空间。
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公开(公告)号：US07496930B2
公开(公告)日：2009-02-24
申请号：US10831575
申请日：2004-04-22
申请人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
发明人： Gerard Chauvel , Serge Lasserre , Dominique D'Inverno , Maija Kuusela , Gilbert Cabillic , Jean-Philippe Lesot , Michel Banâtre , Jean-Paul Routeau , Salam Majoul , Frédéric Parain
IPC分类号： G06F13/00
摘要： In some embodiments, a storage medium comprises application software that performs one or more operations and that directly manages a device. The application software comprises instructions that initialize an application data structure (e.g., an object or array) usable by the application software to manage the device and also comprises instructions that map the application data structure to a memory associated with the device without the use of a device driver. In other embodiments, a method comprises initializing an application data structure to manage a hardware device and mapping the application data structure to a memory associated with the hardware device without the use of a device driver. The application data structure may store a single dimensional data structure or a multi-dimensional data structure. In some embodiments, the device being managed by the application software may comprise a display and the application software may comprise Java code.
摘要翻译： 在一些实施例中，存储介质包括执行一个或多个操作并直接管理设备的应用软件。 应用软件包括初始化应用软件可用于管理设备的应用数据结构（例如，对象或阵列）的指令，还包括将应用数据结构映射到与设备相关联的存储器而不使用 设备驱动。 在其他实施例中，一种方法包括初始化应用数据结构以管理硬件设备，并将应用数据结构映射到与硬件设备相关联的存储器，而不使用设备驱动程序。 应用数据结构可以存储单维数据结构或多维数据结构。 在一些实施例中，由应用软件管理的设备可以包括显示器，并且应用软件可以包括Java代码。
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8.发明申请Method and system to construct a data-flow analyzer for a bytecode verfier 有权构建一个字节码verfier的数据流分析器的方法和系统公开(公告)号：US20060026404A1
公开(公告)日：2006-02-02
申请号：US11188502
申请日：2005-07-25
IPC分类号： G06F9/44
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： The problems noted above are solved in large part by a method and system to construct a data-flow analyzer for a bytecode verifier using existing hardware resources and software. Specifically, micro-sequences and JSM hardware resources may be employed fetch a first instruction, apply the first instruction to a decode logic of a processor, trigger execution of a first series of instructions by the decode logic that pops a first value off of a data structure, such as a stack or local variable map, the first value indicative of a parameter type pushed on the stack or local variable map by a previously decoded instruction; and verify that the first value is a parameter type expected by the first instruction.
摘要翻译： 上述问题在很大程度上是由现有硬件资源和软件构成用于字节码验证器的数据流分析器的方法和系统。 具体来说，可以采用微序列和JSM硬件资源来取得第一指令，将第一指令应用于处理器的解码逻辑，由解码逻辑触发第一系列指令的执行，该解码逻辑从数据中弹出第一值 结构，例如堆栈或局部变量映射，指示通过先前解码的指令来推送在堆栈上的参数类型的第一值或局部变量映射; 并验证第一个值是第一个指令预期的参数类型。
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公开(公告)号：US20060026397A1
公开(公告)日：2006-02-02
申请号：US11116897
申请日：2005-04-28
IPC分类号： G06F9/00
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012 , Y02D10/13
摘要： A processor executes an instruction that causes a source data field from a first source register to be copied to a destination register at a programmable position within the destination register. The instruction is particularly useful for generating media-based bitstreams (e.g., audio, video). In some embodiments, a system (e.g., a communication device such as cellular telephone) includes a processor capable of executing the instruction as described above.
摘要翻译： 处理器执行指令，其使来自第一源寄存器的源数据字段被复制到目的地寄存器中的可编程位置处的目的地寄存器。 该指令对于生成基于媒体的比特流（例如，音频，视频）特别有用。 在一些实施例中，系统（例如，诸如蜂窝电话的通信设备）包括能够执行如上所述的指令的处理器。
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公开(公告)号：US20060026390A1
公开(公告)日：2006-02-02
申请号：US11186315
申请日：2005-07-21
申请人： Gilbert Cabillic , Gerard Chauvel
发明人： Gilbert Cabillic , Gerard Chauvel
IPC分类号： G06F9/30
CPC分类号： G06F12/1081 , G06F9/30174 , G06F9/45504 , G06F12/0802 , G06F2212/6012
摘要： An electronic device comprising decode logic that decodes instructions and a stack coupled to the decode logic. A group of instructions causes the decode logic to push onto the stack, after halting processing of a first thread at a switch point and prior to processing a second thread, a minimum amount of information needed to resume execution of the first thread at the switch point and not information not needed to resume execution of the first thread at the switch point.
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