公开(公告)号：US5742537A

公开(公告)日：1998-04-21

申请号：US833310

申请日：1997-04-04

申请人： Gilbert M. Wolrich ,  Timothy C. Fischer ,  John J. Ellis ,  Patricia L. Kroesen

发明人： Gilbert M. Wolrich ,  Timothy C. Fischer ,  John J. Ellis ,  Patricia L. Kroesen

IPC分类号： G06F7/485 ,  G06F7/50 ,  G06F7/38

CPC分类号： G06F7/485 ,  G06F7/49952

摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

摘要翻译： 描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。 添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，用于从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道的舍入加法器 舞台操作。 舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。 加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。 浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。

公开(公告)号：US6101516A

公开(公告)日：2000-08-08

申请号：US191143

申请日：1998-11-13

申请人： Gilbert M. Wolrich ,  Timothy C. Fischer ,  John J. Ellis

发明人： Gilbert M. Wolrich ,  Timothy C. Fischer ,  John J. Ellis

IPC分类号： G06F5/01 ,  G06F7/50 ,  G06F7/57

CPC分类号： G06F7/483 ,  G06F5/012 ,  G06F7/485 ,  G06F2207/3884 ,  G06F7/4873 ,  G06F7/49952 ,  G06F7/49957

摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

摘要翻译： 描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。 添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，用于从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道中的舍入加法器 舞台操作。 舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。 加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。 浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。

公开(公告)号：US5867407A

公开(公告)日：1999-02-02

申请号：US955087

申请日：1997-10-21

申请人： Gilbert M. Wolrich ,  Timothy C. Fischer ,  John J. Ellis

发明人： Gilbert M. Wolrich ,  Timothy C. Fischer ,  John J. Ellis

IPC分类号： G06F5/01 ,  G06F7/50 ,  G06F7/57

CPC分类号： G06F7/483 ,  G06F5/012 ,  G06F7/485 ,  G06F2207/3884 ,  G06F7/4873 ,  G06F7/49952 ,  G06F7/49957

摘要： A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

摘要翻译： 描述了一种流水线浮点处理器，其包括用于执行浮点加法的添加管。 添加管道包括用于从输入操作数的检查中预测归一化偏移量的电路，从输入操作数确定“粘滞位”的电路，以及将一对操作数相加并将结果舍入到单个管道的舍入加法器 舞台操作。 舍入加法器结合了一系列进位选择加法器的选择逻辑中的舍入的效果。 加法器还使数据路径对齐，以允许经济地存储和检索用于浮点或转换操作的浮点和整数操作数。 浮点处理器还包括在加法器流水线中，除法器电路包括具有溢出商位位置的商寄存器以检测分割操作的结束。

公开(公告)号：US5065379A

公开(公告)日：1991-11-12

申请号：US508039

申请日：1990-04-10

申请人： Stephen P. Smith ,  John J. Ellis

发明人： Stephen P. Smith ,  John J. Ellis

IPC分类号： G06K17/00 ,  G11B17/22

CPC分类号： G11B17/225 ,  G06K17/0012

摘要： In an automated data library comprising a plurality of storage areas each arranged to accept and store a data storage member, a reading device arranged to retrieve data from a data storage member, and carriage means arranged to selectively transfer data storage members between the storage area and the reading device. A lever is disposed along a side of the carriage adjacent the reading and is arranged for movement between a rest portion within the perimeter of the carriage and an extended position whereby the lever engages a data storage member extending from an opening in the reading device to fully insert the member into the device.

摘要翻译： 在包括多个存储区域的自动数据库中，每个存储区域被布置成接收和存储数据存储构件，布置成从数据存储构件检索数据的读取装置和布置成选择性地将数据存储构件在存储区域和 阅读设备。 杠杆沿着支架的与读数相邻的一侧设置，并且布置成用于在托架的周边内的搁置部分和延伸位置之间运动，从而杠杆接合从读取装置中的开口延伸到完全的数据存储构件 将成员插入设备。