摘要:
In one embodiment, a central processing unit (CPU) includes multiple clock zones. Each clock zone includes at least one sensor that generates a signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, a first controller for controlling a frequency of operation of the clock generator in response to the at least one sensor, wherein the first controller further controls the frequency of operation in response to communication of frequency adjustments from first controllers in other clock zones within one cycle of latency, and a second controller that provides an overdrive signal, that is combined with adjustment signals from the first controller for the clock generator, in response to communication of frequency adjustments from other clock zones beyond one cycle of latency.
摘要:
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要:
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要:
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要:
A pipelined floating point processor including an add pipe for performing floating point additions described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and interger operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要:
One embodiment of the invention comprises, in each clock zone of a central processing unit, at least one sensor that generates a power signal indicative of a power supply voltage within the clock zone, a clock generator for providing a variable frequency clock to the clock zone, and a controller for controlling an operating frequency of the clock generator in response to the power signal and in response to frequency adjustment communications from other clock zones.
摘要:
A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and integer operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.
摘要:
In a preferred embodiment, the invention provides a method and system for allowing a frequency synthesizer to function despite long delays. A first and second phase comparator, each with at least three inputs and an output are preset to a predetermined logical value by a first control circuit. A first signal is connected to an input of the first and second phase comparators. A second signal is connected to a second input of the second phase comparator and to the input of a programmable dead zone delay circuit. The output of the programmable dead zone delay circuit is connected to a second input of the first phase comparator. A preset value, determined by the first control circuit, is presented on the outputs of the first and second phase comparators. Until metastability is resolved, these outputs retain a valid fail-safe default.
摘要:
A computer hardware system is disclosed for determining during a single clock cycle whether a data buffer having a plurality of entries can accept additional data. The system has multiple stages, having one or more adders/encoders that process the data buffer entries' valid bits in parallel. Groups of entries are associated with first-stage adders/encoders. Valid bits and their complements for entries in each group are received into multiple first-stage adders that compute and output encoded values indicating the number of available entries within each group, or first-stage totals. The adders also encode the first-stage totals such that a saturated count corresponds to a pre-charged state of the first-stage adder. The first-stage totals are then sent to additional stages having adders/encoders that are substantially the same as the first-stage adders/encoders. The additional-stage adders combine the encoded totals from prior stages and determine whether the buffer has available entries.
摘要:
Systems and methods of edge calibration for synchronous data transfer between clock domains are disclosed. An exemplary method may comprise comparing a drive clock signal to a receive clock signal, generating a select clock signal, and configuring a data path based a least in part on the select clock signal for synchronous data transfer between clock domains so that data arrives in an early clock domain at the desired logical clock cycle.