公开(公告)号：US08312409B1

公开(公告)日：2012-11-13

申请号：US12718945

申请日：2010-03-05

申请人： Gitu Jain ,  Vinay Verma ,  Taneem Ahmed ,  Sandor S. Kalman ,  Sanjeev Kwatra ,  Christopher H. Kingsley ,  Jason H. Anderson ,  Satyaki Das

发明人： Gitu Jain ,  Vinay Verma ,  Taneem Ahmed ,  Sandor S. Kalman ,  Sanjeev Kwatra ,  Christopher H. Kingsley ,  Jason H. Anderson ,  Satyaki Das

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5054

摘要： A method is described that includes: determining that nets of the circuit design comprise overlap, where the overlap indicates that at least two of the nets of the circuit design use a same routing resource; dividing the nets with overlap among a plurality of buckets, where for each bucket, a net of the bucket does not overlap any other net in the bucket; sequentially processing each bucket by unrouting and rerouting, via at least one processor, nets in the bucket; and storing routing information specifying routes for nets of the circuit design.

摘要翻译： 描述了一种方法，其包括：确定电路设计的网络包括重叠，其中重叠指示电路设计的网络中的至少两个使用相同的路由资源; 在多个桶之间用重叠划分网，其中对于每个桶，桶的网不与桶中的任何其他网重叠; 通过至少一个处理器，通过在桶中的网络进行路由和重新路由来顺序地处理每个桶; 并存储指定电路设计网络的路由的路由信息​​。

公开(公告)号：US08155907B1

公开(公告)日：2012-04-10

申请号：US12480488

申请日：2009-06-08

申请人： Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

发明人： Austin H. Lesea ,  Stephen M. Trimberger ,  Christopher H. Kingsley ,  Satyaki Das ,  Tim Tuan

IPC分类号： G06F11/00 ,  G06F19/00 ,  G06F17/40

CPC分类号： G06F17/5045 ,  G06F11/26 ,  G06F2217/86

摘要： Methods of enabling functions of a design to be implemented in an integrated circuit device are disclosed. An exemplary method comprises applying test data to a plurality of dice having different element types for implementing circuits, wherein the plurality of dice have a common layout of the different element types for implementing the circuits; receiving output data from the plurality of dice in response to applying the test data to the plurality of dice; analyzing the output data from the plurality of dice; transforming by a computer the output data to characterization data comprising timing data associated with the different element types for implementing circuits, wherein the characterization data comprises data associated with regions of the dice, and storing the characterization data. A computer program product for enabling functions of a design to be implemented in an integrated circuit device is also disclosed.

摘要翻译： 公开了在集成电路装置中实现设计功能的方法。 示例性方法包括将测试数据应用于具有用于实现电路的不同元件类型的多个骰子，其中所述多个骰子具有用于实现电路的不同元件类型的公共布局; 响应于将所述测试数据应用于所述多个骰子，从所述多个骰子接收输出数据; 分析来自多个骰子的输出数据; 通过计算机将输出数据转换成包括与用于实现电路的不同元件类型相关联的定时数据的表征数据，其中表征数据包括与骰子区域相关联的数据，并存储表征数据。 还公开了一种用于使得能够在集成电路器件中实现设计功能的计算机程序产品。

公开(公告)号：US08136075B1

公开(公告)日：2012-03-13

申请号：US12267058

申请日：2008-11-07

申请人： Satyaki Das ,  Christopher H. Kingsley

发明人： Satyaki Das ,  Christopher H. Kingsley

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5077

摘要： A multilevel shared database for routing for an integrated circuit is described. An aspect relates generally to a database comprising routing edges defined by tile templates. The routing edges are associated with a plurality of wire length segmentations. The tile templates are associated with tiles of an integrated circuit. The tiles are repeated circuit blocks forming an array. A portion of the tile templates are shared among a portion of the tiles such that the tile templates are less in number than the tiles. The tile templates are associated with pointers for pointing to wire templates.

摘要翻译： 描述了用于集成电路的路由的多级共享数据库。 一个方面一般涉及包括由瓦片模板定义的路由边缘的数据库。 路由边缘与多个线长度分段相关联。 瓦片模板与集成电路的瓦片相关联。 瓦片是形成阵列的重复电路块。 瓦片模板的一部分在瓦片的一部分之间共享，使得瓦片模板的数量少于瓦片。 瓦片模板与指向线模板的指针相关联。

公开(公告)号：US07636907B1

公开(公告)日：2009-12-22

申请号：US11805744

申请日：2007-05-24

申请人： Satyaki Das ,  Yu Hu

发明人： Satyaki Das ,  Yu Hu

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A computer-implemented method of balancing logic resource usage in a circuit design for a programmable logic device (PLD) can include determining that an assignment of elements of the circuit design to a first type of logic resource of the PLD is unbalanced compared to an assignment of elements of the circuit design to an alternate type of logic resource of the PLD. An Integer Linear Programming (ILP) formulation specifying a balanced assignment of elements to the first and alternate types of logic resources can be generated. A solution for the ILP formulation can be obtained. Selected elements of the circuit design can be re-mapped from the first type of logic resource to the alternate type of logic resource according to the solution of the ILP formulation and the circuit design specifying the re-mapped elements can be output.

摘要翻译： 用于平衡用于可编程逻辑器件（PLD）的电路设计中的逻辑资源使用的计算机实现的方法可以包括确定与分配方式相比，PLD的第一类逻辑资源的电路设计的元素的分配不平衡 的电路设计的元素到PLD的替代类型的逻辑资源。 可以生成整数线性规划（ILP）公式，其指定元素对第一和另一类逻辑资源的均衡分配。 可以获得ILP制剂的溶液。 可以根据ILP公式的解决方案将电路设计的选定元件从第一类型的逻辑资源重新映射到替代类型的逻辑资源，并且可以输出指定重新映射的元件的电路设计。

公开(公告)号：US07477073B1

公开(公告)日：2009-01-13

申请号：US11454316

申请日：2006-06-16

申请人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

发明人： Tim Tuan ,  Arifur Rahman ,  Satyaki Das ,  Sean W. Kao

IPC分类号： H03K19/177 ,  H03K19/0175

CPC分类号： H03K19/17736 ,  H03K19/17784

摘要： A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.

摘要翻译： PLD利用异构架构来降低其活动资源的功耗。 PLD的可编程资源分为第一分区和第二分区，其中第一分区的资源被优化用于低功耗，并且第二分区的资源被优化用于高性能。 包含非关键定时路径的用户设计的部分被映射到由功率优化的第一分区的资源并由其实现，并且包含关键定时路径的用户设计的部分被映射到由性能优化的资源实现 第二分区。

公开(公告)号：US07788624B1

公开(公告)日：2010-08-31

申请号：US12579870

申请日：2009-10-15

申请人： Satyaki Das ,  Yu Hu

发明人： Satyaki Das ,  Yu Hu

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A computer-implemented method of balancing logic resource usage in a circuit design for a programmable integrated circuit (IC) includes determining that an assignment of elements of the circuit design to a first type of logic resource is unbalanced compared to an assignment of elements to an alternate type of logic resource. Binary variables are defined for circuit elements assigned to the first and alternate types of logic resources, where each binary variable indicates whether the associated circuit element is to be re-assigned to the first or alternate type of logic resource. Constraints are defined specifying relationships among selected variables. Values for the variables are obtained according to the constraints by minimizing a function dependent on a sum of the binary variables. Circuit elements are re-assigned to the first or alternate types of logic resources according to the values determined for the binary variables, and the circuit design is output.

摘要翻译： 在用于可编程集成电路（IC）的电路设计中平衡逻辑资源使用的计算机实现的方法包括确定与元素的分配相比，电路设计的元件对第一类型的逻辑资源的分配是不平衡的 备用类型的逻辑资源。 二进制变量被定义为分配给第一和另一类逻辑资源的电路元件，其中每个二进制变量指示相关的电路元件是否被重新分配给第一或另一类逻辑资源。 定义约束条件指定所选变量之间的关系。 根据约束通过使取决于二进制变量之和的函数最小化来获得变量的值。 根据为二进制变量确定的值，将电路元件重新分配给第一种或其他类型的逻辑资源，并输出电路设计。

公开(公告)号：US07831943B1

公开(公告)日：2010-11-09

申请号：US11787600

申请日：2007-04-16

申请人： Satyaki Das

发明人： Satyaki Das

IPC分类号： G06F17/50

CPC分类号： G06F17/5054

摘要： A method of determining validity of slice packing for a programmable device can include identifying a slice topology for a slice, identifying a circuit fragment assigned to the slice, and generating a set of Boolean equations describing conditions for mapping the circuit fragment to the slice according to the slice topology. The method further can include determining whether a solution to the set of Boolean equations exists and indicating whether the slice is validly packed according to whether a solution for the set of Boolean equations is determined.

摘要翻译： 确定可编程设备的片包装的有效性的方法可以包括识别切片的切片拓扑，识别分配给切片的电路片段，以及生成一组布尔方程，其描述根据片段将电路片段映射到切片的条件 切片拓扑。 该方法还可以包括确定是否存在一组布尔方程组的解，并且根据是否确定一组布尔方程的解来指示切片是否被有效地打包。

公开(公告)号：US07389485B1

公开(公告)日：2008-06-17

申请号：US11390925

申请日：2006-03-28

申请人： Anirban Rahut ,  Satyaki Das ,  Arifur Rahman

发明人： Anirban Rahut ,  Satyaki Das ,  Arifur Rahman

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F17/5054 ,  G06F2217/78

摘要： Methods of routing user designs in programmable logic devices (PLDs) having heterogeneous routing structures, i.e., PLDs including both high-power and low-power interconnect resources. A first pass routing step is performance-based, e.g., utilizes a cost function biased towards the high-power interconnect resources. The first routed design is then evaluated to identify non-critical nets in the first routed design that can yield the most power-saving benefit by being retargeted to the low-power interconnect resources. For example, a sorted list of nets can be created in which the identified nets are evaluated based on the capacitance per load pin of each net. A second pass routing step is then performed, e.g., rerouting the nets identified as being non-critical and having the greatest potential power-saving benefit. In some embodiments, the permitted increase in the delay of each rerouted net is bound by the slack of the net as routed in the first routed design.

摘要翻译： 在具有异构路由结构的可编程逻辑设备（PLD）中路由用户设计的方法，即包括大功率和低功率互连资源的PLD。 第一路由路由步骤是基于性能的，例如，利用偏向大功率互连资源的成本函数。 然后评估第一路由设计以识别第一路由设计中的非关键网络，其可以通过重定向到低功率互连资源来产生最节能的优点。 例如，可以创建网络的排序列表，其中基于每个网络的每个负载引脚的电容来评估所识别的网络。 然后执行第二通路由步骤，例如重新路由被识别为非关键并且具有最大潜在省电优点的网络。 在一些实施例中，允许的每个重新路由网络的延迟增加受到在第一路由设计中路由的网络的松弛的约束。