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    Incremental placement and routing
    1.
    发明授权
    Incremental placement and routing 有权
    增量放置和布线

    公开(公告)号：US08196081B1

    公开(公告)日：2012-06-05

    申请号：US12751175

    申请日：2010-03-31

    申请人： Hasan Arslan ,  Vinay Verma ,  Sandor Kalman

    发明人： Hasan Arslan ,  Vinay Verma ,  Sandor Kalman

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5077 ,  G06F17/5072 ,  G06F2217/06

    摘要： In one embodiment of the invention, a processor-implemented method is provided for routing of a partially routed circuit design. Modified signals of the partially routed circuit design are determined. A first set of routing constraints are applied by the processor to the unmodified signals of the circuit design. For each logic block of the circuit design, the number of the modified signals and the number of the unmodified signals connected to the logic block are determined. In response to one of the logic blocks having a ratio of the number of modified signals to the number of unmodified signals greater than a threshold ratio, the routing constraints are removed by the processor from one or more of the unmodified signals of the one of the logic blocks. The partially routed circuit design is then routed by the processor according to the remaining routing constraints, and the resulting netlist is stored.

    摘要翻译： 在本发明的一个实施例中，提供了一种处理器实现的方法来路由部分路由的电路设计。 确定部分路由电路设计的修改信号。 处理器将第一组路由约束应用于电路设计的未修改信号。 对于电路设计的每个逻辑块，确定修改的信号的数量和连接到逻辑块的未修改信号的数量。 响应于具有大于阈值比率的修改信号的数量与未修改信号的数量的比率的逻辑块之一，处理器从一个或多个未修改信号中的一个或多个的未修改信号中去除路由约束 逻辑块。 部分路由的电路设计然后由处理器根据剩余的路由约束进行路由，并且存储所得到的网表。

    Parallel process optimized signal routing
    2.
    发明授权
    Parallel process optimized signal routing 有权
    并行过程优化信号路由

    公开(公告)号：US08250513B1

    公开(公告)日：2012-08-21

    申请号：US12939765

    申请日：2010-11-04

    申请人： Vinay Verma ,  Gitu Jain ,  Sanjeev Kwatra ,  Taneem Ahmed ,  Sandor S. Kalman

    发明人： Vinay Verma ,  Gitu Jain ,  Sanjeev Kwatra ,  Taneem Ahmed ,  Sandor S. Kalman

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5077 ,  G06F2217/08

    摘要： In one embodiment, a method for routing of a circuit design netlist is provided. A processing cost is determined for each net in the netlist. A plurality of regions are defined for the target device such that the total processing costs of nets are balanced between the plurality of regions. Concurrent with routing one or more nets of a first one of the plurality of regions, one or more nets are routed in at least one other of the plurality of regions. Synchronization and subsequent routing are performed for unrouted nets of the netlist.

    摘要翻译： 在一个实施例中，提供了一种用于路由电路设计网表的方法。 网表中的每个网络确定处理成本。 为目标设备定义多个区域，使得网络的总处理成本在多个区域之间平衡。 与路由多个区域中的第一个区域的一个或多个网络同时，在多个区域中的至少另一个区域中路由一个或多个网络。 为网表的未路由网络执行同步和后续路由。

    Patterns for routing nets in a programmable logic device
    3.
    发明授权
    Patterns for routing nets in a programmable logic device 有权
    用于在可编程逻辑器件中路由网络的模式

    公开(公告)号：US07797665B1

    公开(公告)日：2010-09-14

    申请号：US11999559

    申请日：2007-12-06

    申请人： Hui Xu ,  Vinay Verma ,  Anirban Rahut ,  Jason H. Anderson ,  Sandor S. Kalman

    发明人： Hui Xu ,  Vinay Verma ,  Anirban Rahut ,  Jason H. Anderson ,  Sandor S. Kalman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： Nets of a logic design are efficiently routed in a programmable logic device, which includes multiple types of programmable interconnects. Patterns are read from a library in a storage device. Each pattern includes an ordered set of the types of the programmable interconnects. A path is determined from the source to the destination for each net of the logic design. The path is through a sequence of the programmable interconnects having types that correspond to each type in the ordered set of a selected pattern. A description is output of the path for each of the nets.

    摘要翻译： 逻辑设计的网络可编程逻辑器件有效路由，可编程逻辑器件包括多种类型的可编程互连。 从存储设备中的库中读取模式。 每个模式包括可编程互连类型的有序集合。 对于逻辑设计的每个网络，从源到目的地确定路径。 该路径通过可编程互连序列，其具有对应于所选模式的有序集合中的每种类型的类型。 描述是每个网络的路径的输出。

    Incremental routing in integrated circuit design
    4.
    发明授权
    Incremental routing in integrated circuit design 有权
    集成电路设计中的增量路由

    公开(公告)号：US07134112B1

    公开(公告)日：2006-11-07

    申请号：US10624615

    申请日：2003-07-21

    申请人： Jason H. Anderson ,  Vinay Verma ,  Sandor S. Kalman

    发明人： Jason H. Anderson ,  Vinay Verma ,  Sandor S. Kalman

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077

    摘要： A method for completing the routing of a partially routed design is provided. The unrouted pins are routed to generate a first plurality of nets that may contain shorts or overlaps between the nets. The nets are analyzed to obtain timing information, and then divided into a set of critical and a set of non-critical nets. The non-critical nets are hidden, and the critical nets are rerouted to remove overlaps. The non-critical nets are then unhidden. The non-critical nets and rerouted critical nets are then rerouted so as to remove overlaps.

    摘要翻译： 提供了完成部分路由设计路由的方法。 未路由的引脚被路由以产生可以在网之间包含短路或重叠的第一多个网。 对网络进行分析以获得定时信息，然后分为一组关键网络和一组非关键网络。 非关键网络被隐藏，关键网络被重新路由以消除重叠。 然后，非关键网络将被禁止。 然后重新路由非关键网络和重新路由的关键网络，以消除重叠。

    Post-layout optimization in integrated circuit design
    5.
    发明授权
    Post-layout optimization in integrated circuit design 有权
    集成电路设计后布局优化

    公开(公告)号：US07111268B1

    公开(公告)日：2006-09-19

    申请号：US10644132

    申请日：2003-08-20

    申请人： Jason H. Anderson ,  Sandor S. Kalman ,  Vinay Verma

    发明人： Jason H. Anderson ,  Sandor S. Kalman ,  Vinay Verma

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5072 ,  G06F17/5077

    摘要： A method for post-layout timing optimization is disclosed. The method performs timing analysis on a design to obtain timing information such as critical paths and slack values. Incremental placement based on the timing information is performed. A new routed design is generated by applying incremental routing to the result of incremental placement. The routed design is stored if its performance is better than the previous routed design. The above steps are repeated until a predetermined criterion is met.

    摘要翻译： 公开了一种布局后定时优化的方法。 该方法对设计执行定时分析以获得诸如关键路径和松弛值的定时信息。 执行基于定时信息的增量放置。 通过将增量路由应用于增量放置结果来生成新的路由设计。 如果路由设计的性能优于先前的路由设计，则存储路由设计。 重复上述步骤直到满足预定标准。

    Parallel signal routing
    8.
    发明授权
    Parallel signal routing 有权
    并行信号路由

    公开(公告)号：US08201130B1

    公开(公告)日：2012-06-12

    申请号：US12939732

    申请日：2010-11-04

    申请人： Sandor S. Kalman ,  Vinay Verma ,  Gitu Jain ,  Taneem Ahmed ,  Sanjeev Kwatra

    发明人： Sandor S. Kalman ,  Vinay Verma ,  Gitu Jain ,  Taneem Ahmed ,  Sanjeev Kwatra

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5077 ,  G06F17/5054

    摘要： A method is provided for routing a circuit design netlist. Nets of the netlist are grouped into a plurality of sub-netlists. For each sub-netlist, nets of the sub-netlist are routed as a function of congestion between nets of the sub-netlist. Congestion between nets of other sub-netlists in the plurality of sub-netlists is not taken into account. If two or more nets of the netlist are routed through the same routing resource, a global congestion history data set is updated to describe congestion between all nets in the netlist, and the two or more nets of the netlist are unrouted. The two or more nets are each rerouted as a function of the global congestion history data set and congestion between nets of the same sub-netlist as the net.

    摘要翻译： 提供了一种用于布线电路设计网表的方法。 网表的网络被分组成多个子网表。 对于每个子网表，子网表的网络作为子网表的网络之间的拥塞的功能被路由。 不考虑多个子网表中其他子网表的网络之间的拥塞。 如果网表的两个或多个网络通过相同的路由资源路由，则更新全局拥塞历史数据集，以描述网表中所有网之间的拥塞，并且网表的两个或多个网是未路由的。 两个或更多个网络每个被重新路由为全局拥塞历史数据集的功能和与网络相同的子网表的网络之间的拥塞。