-
公开(公告)号：US20210203496A1
公开(公告)日：2021-07-01
申请号：US17136775
申请日：2020-12-29
摘要： Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums for providing a secure method of modifying, erasing, or updating security keys for protected regions of a memory device by using a special firmware object (a key-modification firmware) loaded to the memory device that contains instructions to reprogram, modify, and/or erase the keys. To ensure that this key-modification firmware does not become a security risk, the key-modification firmware object may be protected from subsequent usage in a variety of ways.
-
公开(公告)号：US20200005880A1
公开(公告)日：2020-01-02
申请号：US16022959
申请日：2018-06-29
申请人： Giuseppe Cariello , Antonino Pollio , Fulvio Rori
发明人： Giuseppe Cariello , Antonino Pollio , Fulvio Rori
摘要： A memory device comprises a memory array including multi-level memory cells, buffer circuitry, a memory control unit and a program progress indicator. The memory control unit is operatively coupled to the memory array and configured to load first data into the buffer circuitry and program the multi-level memory cells with the first data using multiple programming passes to program multiple programming levels. The program progress indicator is configured to indicate completion of a programming level as the programming of the multiple programming levels progresses. The memory control unit is further configured to load second data for programming of the multi-level memory cells according to an indication of completion of the program progress indicator.
-
公开(公告)号：US20190065331A1
公开(公告)日：2019-02-28
申请号：US15690903
申请日：2017-08-30
申请人： Harish Singidi , Giuseppe Cariello , Deping He , Scott Anthony Stoller , Devin Batutis , Preston Thomson
发明人： Harish Singidi , Giuseppe Cariello , Deping He , Scott Anthony Stoller , Devin Batutis , Preston Thomson
IPC分类号： G06F11/20
CPC分类号： G06F11/2094 , G06F11/1068 , G06F2201/82 , G11C16/0483 , G11C16/349 , G11C29/832 , G11C29/883
摘要： Devices and techniques for a flash memory block retirement policy are disclosed herein. In an example embodiment, a first memory block is removed from service in response to encountering a read error in the first memory block that exceeds a first error threshold. Recoverable data is copied from the first memory block to a second memory block. During each of multiple iterations, the first memory block is erased and programmed, and each page of the first memory block is read. In response to none of the pages exhibiting a read error that exceeds a second error threshold during the multiple iterations, the first memory block is returned to service.
-
公开(公告)号：US20200210067A1
公开(公告)日：2020-07-02
申请号：US16236040
申请日：2018-12-28
IPC分类号： G06F3/06
摘要： Devices and techniques for adjustable memory device write performance are described herein. An accelerated write request can be received at a memory device from a controller of the memory device. The memory device can identify that a target block for external writes is opened as a multi-level cell block. The memory device can then write data for the accelerated write request to the target block using a single-level cell encoding.
-
公开(公告)号：US20200004453A1
公开(公告)日：2020-01-02
申请号：US16024428
申请日：2018-06-29
申请人： Fulvio Rori , Giuseppe Cariello
发明人： Fulvio Rori , Giuseppe Cariello
IPC分类号： G06F3/06
摘要： A variety of applications can include memory systems that have one or more memory devices capable of performing memory operations on multiple blocks of memory in response to a command from a host. For example, improvement in erase performance can be attained by erasing multiple blocks of memory by one of a number of approaches. Such approaches can include parallel erasure followed by serial verification in response to a single command. Other approaches can include sequential erase and verify operations of the multiple blocks in response to a single command. Additional apparatus, systems, and methods are disclosed.
-
-
-
-
搜索结果
5 条记录 (耗时 0.03 秒)
