公开(公告)号：US06442617B1

公开(公告)日：2002-08-27

申请号：US09282311

申请日：1999-03-31

申请人： Glen H. Lowe ,  Edmund Chen ,  Claude G. Hayek

发明人： Glen H. Lowe ,  Edmund Chen ,  Claude G. Hayek

IPC分类号： G06F1516

CPC分类号： G06F13/385

摘要： A method and system for filtering multicast packets by a peripheral component. In one embodiment, the present invention uses a peripheral component driver to store in memory a selected hash values corresponding to desired multicast packets. In one embodiment, the peripheral component driver operates on a host computer to which a peripheral component is coupled. Next, when the peripheral component receives an incoming multicast packet, the present invention uses a hash value generator disposed on the peripheral component to determine a hash value for the received multicast packet. The present embodiment then compares the hash value for the received multicast packet with the selected hash values stored in memory. Provided the hash value for the received multicast packet does not match any of the selected hash values stored in the memory, the present embodiment discards the received multicast packet without interrupting the host computer. In so doing, the present embodiment effectively filters multicast packets without requiring constant intervention by the CPU (central processing unit) of the host computer.

摘要翻译： 一种外围组件对组播数据包进行过滤的方法和系统。 在一个实施例中，本发明使用外围组件驱动程序在存储器中存储对应于期望的多播分组的所选哈希值。 在一个实施例中，外围组件驱动器在外围组件耦合到的主计算机上操作。 接下来，当外围组件接收到输入的组播分组时，本发明使用设置在外围组件上的散列值生成器来确定接收的组播分组的散列值。 然后，本实施例将所接收的多播分组的哈希值与存储在存储器中的所选哈希值进行比较。 如果接收到的组播数据包的散列值与存储器中存储的所选哈希值中的任一个不匹配，则本实施例在不中断主计算机的情况下丢弃所接收的组播数据包。 这样做，本实施例有效地过滤组播分组，而不需要主计算机的CPU（中央处理单元）的持续干预。

公开(公告)号：US06192440B1

公开(公告)日：2001-02-20

申请号：US09258501

申请日：1999-02-26

申请人： Glen H. Lowe ,  Edmund Chen

发明人： Glen H. Lowe ,  Edmund Chen

IPC分类号： G06F1324

CPC分类号： G06F13/24 ,  G06F2213/2406

摘要： A system and method for dynamically calculating the maximum amount of time a peripheral component event can be stored before generating a corresponding interrupt. Specifically, in this embodiment, the host computer is adapted to have a peripheral component removably coupled thereto and is adapted to operate a peripheral component driver. The peripheral component driver, in turn, is adapted to dynamically calculate the maximum amount of time a peripheral component event can be stored before generating a corresponding interrupt. The peripheral component of this embodiment is adapted to store the peripheral component event and cause the generation of an interrupt when the peripheral component event has been stored for the maximum amount of time. Once again, the present embodiment, like the previous embodiments, reduces the frequency with which interrupts are generated, and minimizes the CPU overhead associated with the servicing of interrupts.

摘要翻译： 一种用于在产生相应中断之前动态计算外围组件事件可以被存储的最大时间量的系统和方法。 具体来说，在本实施例中，主计算机适于具有可移除地耦合到其上的外围部件，并适于操作外围部件驱动器。 外围组件驱动器又适用于在产生相应的中断之前动态地计算外围组件事件可以被存储的最大时间量。 本实施例的外围组件适用于存储周边组件事件，并且当周边组件事件已经被存储了最大时间量时引起中断的产生。 再次，与前述实施例一样，本实施例减少了产生中断的频率，并且使与中断服务相关联的CPU开销最小化。

公开(公告)号：US06189067B1

公开(公告)日：2001-02-13

申请号：US09258514

申请日：1999-02-26

申请人： Glen H. Lowe ,  Edmund Chen

发明人： Glen H. Lowe ,  Edmund Chen

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： A system and method for dynamically calculating the quantity of peripheral component events to coalesce. In one embodiment, a host computer is adapted to have a peripheral component removably coupled thereto. The host computer is further adapted to operate a peripheral component driver. The peripheral component driver of the present embodiment is adapted to dynamically determine the quantity of peripheral component events to coalesce. The peripheral component is adapted to coalesce the determined quantity of the peripheral component events. Furthermore, the peripheral component is adapted to cause the generation of an interrupt upon the occurrence of the determined quantity of the peripheral component events. Also, the present embodiment periodically re-determines the quantity of the peripheral components which should be coalesced. As a result, the present invention dynamically optimizes the frequency with which interrupts are generated, thereby minimizing the CPU overhead associated with the servicing of interrupts.

摘要翻译： 一种用于动态计算外围组件事件数量以合并的系统和方法。 在一个实施例中，主计算机适于具有可移除地耦合到其上的外围部件。 主计算机还适于操作外围部件驱动器。 本实施例的外围部件驱动器适于动态地确定外围组件事件的数量以合并。 外围组件适于聚合确定的外围组件事件数量。 此外，周边组件适于在发生所确定的外围组件事件数量时产生中断。 此外，本实施例周期性地重新确定应该合并的外围部件的数量。 结果，本发明动态优化产生中断的频率，从而最小化与中断服务相关联的CPU开销。

公开(公告)号：US06189066B1

公开(公告)日：2001-02-13

申请号：US09258500

申请日：1999-02-26

申请人： Glen H. Lowe ,  Edmund Chen

发明人： Glen H. Lowe ,  Edmund Chen

IPC分类号： G06F1324

CPC分类号： G06F13/24

摘要： A system and method for dynamically calculating a maximum allowable time interval which can lapse between peripheral component events before an interrupt is generated. In this embodiment, the host computer is adapted to have a the peripheral component removably coupled thereto and operate a peripheral component driver. The peripheral component driver in this embodiment is adapted to dynamically calculate a maximum allowable time interval which can lapse between peripheral component events before an interrupt is generated. The peripheral component is correspondingly adapted to cause the generation of an interrupt when the maximum allowable time interval has elapsed between successive ones of the peripheral component events. As a result, the present embodiment, like the previous embodiment, reduces the frequency with which interrupts are generated, and minimizes the CPU overhead associated with the servicing of interrupts.

摘要翻译： 一种用于动态计算在产生中断之前可能在外围组件事件之间流逝的最大允许时间间隔的系统和方法。 在该实施例中，主计算机适于具有可移除地耦合到其上的外围部件并操作外围部件驱动器。 本实施例中的外围部件驱动器适于动态地计算在产生中断之前可能在外围组件事件之间流逝的最大允许时间间隔。 相应地，周边部件适于在连续的外围部件事件之间经过最大允许时间间隔时引起中断的产生。 因此，与前述实施例相同，本实施例减少了产生中断的频率，并且使与中断服务相关联的CPU开销最小化。

公开(公告)号：US06643710B1

公开(公告)日：2003-11-04

申请号：US09398351

申请日：1999-09-17

申请人： Leslie Thorne ,  Glen H. Lowe ,  Gary Takashi

发明人： Leslie Thorne ,  Glen H. Lowe ,  Gary Takashi

IPC分类号： G06F1516

CPC分类号： H04L69/16 ,  H04L69/12 ,  H04L69/161 ,  H04L69/163 ,  H04L69/166

摘要： Architecture to fragment transmitted transmission control protocol (TCP) packets to a requested window size. Specifically, one embodiment of the present invention includes a method for implementing transmission control protocol segmentation within hardware. The method includes the hardware, implemented step of downloading a payload header of a data payload stored within memory of a host device. Furthermore, the method also includes the hardware implemented step of downloading a plurality of data segments of the data payload. Additionally, the method includes the hardware implemented step of repeatedly modifying the payload header in order to generate a plurality of frame headers which correspond to the plurality of data segments.

摘要翻译： 将发送的传输控制协议（TCP）数据包分段到所请求的窗口大小的架构。 具体地，本发明的一个实施例包括用于在硬件内实现传输控制协议分段的方法。 该方法包括硬件，下载存储在主机设备的存储器内的数据有效负载的有效载荷报头的实施步骤。 此外，该方法还包括硬件实现的下载数据有效载荷的多个数据段的步骤。 此外，该方法包括硬件实现的步骤，重复修改有效负载报头以便生成对应于多个数据段的多个帧报头。

公开(公告)号：US06704325B1

公开(公告)日：2004-03-09

申请号：US09287229

申请日：1999-04-06

申请人： Glen H. Lowe ,  Claude Hayek

发明人： Glen H. Lowe ,  Claude Hayek

IPC分类号： H04J316

CPC分类号： H04J3/0608

摘要： A method and system for efficiently handling a particular streaming data packet regardless of whether the streaming data packet has a first alignment or a second alignment. In one embodiment, the present invention receives a first portion of an incoming packet stream at a peripheral component adapted to be coupled to a host computer. The present embodiment then receives a second portion of the incoming packet stream at the peripheral component. Next, the present embodiment determines whether the incoming packet stream has a first alignment or a second alignment. Provided that the incoming packet stream has the second alignment, the present embodiment reconfigures the incoming packet stream to have the first alignment. The present embodiment then handles the incoming packet stream using a single processing unit adapted to handle only packet streams having the first alignment. In so doing, the present invention is able to handle an incoming packet stream having either a first alignment or a second alignment without requiring multiple processing units.

摘要翻译： 一种用于有效地处理特定流数据分组的方法和系统，而不管流数据分组是否具有第一对准或第二对准。 在一个实施例中，本发明在适于耦合到主计算机的外围组件处接收输入分组流的第一部分。 然后，本实施例在外围组件处接收输入分组流的第二部分。 接下来，本实施例确定输入分组流是否具有第一对准或第二对准。 如果输入分组流具有第二对准，则本实施例重新配置输入分组流以具有第一对准。 本实施例然后使用适于仅处理具有第一对准的分组流的单个处理单元处理输入分组流。 在这样做时，本发明能够处理具有第一对准或第二对准的输入分组流，而不需要多个处理单元。

公开(公告)号：US6016513A

公开(公告)日：2000-01-18

申请号：US25960

申请日：1998-02-19

申请人： Glen H. Lowe

发明人： Glen H. Lowe

IPC分类号： G06F13/12 ,  H04L29/12 ,  G06F13/00

CPC分类号： H04L61/00 ,  G06F13/128 ,  H04L29/12009

摘要： A method of preventing packet loss when data packets are transferred from a network interface card to a host operating system of a computer. Incoming data packets received by the network interface card are processed in bursts of N data packets, where N is a maximum number of data packets that can be handled by the host operating system. At the end of each burst, a signal is sent to the host operating system that the burst constitutes all the incoming data packets. In one embodiment of the present invention, the signal, which falsely indicates that the transaction is complete, also enables the host operating system to receive another burst of the data packets. The process may be repeated until all the incoming data packets are received by the host operating system. In another embodiment of the present invention, after processing a burst of N data packets, a future hardware interrupt is scheduled and a signal falsely indicating that the burst constitutes all of the incoming data packets is sent. The future hardware interrupt, coupled with the signal, enables the host operating system to receive a stream of data packets without packet loss.

摘要翻译： 当数据分组从网络接口卡传送到计算机的主机操作系统时，防止分组丢失的方法。 网络接口卡接收的接收数据包以N个数据包的突发处理，其中N是主机操作系统可以处理的数据包的最大数量。 在每个突发结束时，信号被发送到主机操作系统，突发构成所有输入的数据分组。 在本发明的一个实施例中，错误地指示事务完成的信号还使得主机操作系统能够接收数据分组的另一突发。 该过程可以重复，直到所有的输入数据分组被主机操作系统接收。 在本发明的另一个实施例中，在处理N个数据分组的突发之后，调度未来的硬件中断，并发送错误地指示突发构成所有输入数据分组的信号。 未来的硬件中断，加上信号，使得主机操作系统能够接收到数据流，而不会丢包。

公开(公告)号：US07051226B1

公开(公告)日：2006-05-23

申请号：US09371463

申请日：1999-08-10

申请人： Glen H. Lowe ,  Leslie Thorne ,  Gary Takushi

发明人： Glen H. Lowe ,  Leslie Thorne ,  Gary Takushi

IPC分类号： G06F1/14

CPC分类号： H04L47/13 ,  H04L47/10 ,  H04L47/11 ,  H04L2012/445

摘要： A method and system for providing priority to a station in a congested half duplex Ethernet network. Specifically, one embodiment of the present invention includes a method for providing priority to a peripheral component (e.g., half duplex Network Interface Card) in a congested network. The method includes the step of detecting a collision of a data packet during transmission of the data packet by a peripheral component coupled to a network. Furthermore, the method includes the step of determining a restricted back off time. It should be appreciated that the restricted back off time is substantially equal to or less than a restricted time value. Additionally, the method includes the step of causing the peripheral component to wait the restricted back off time before trying to retransmit the data packet over the network.

摘要翻译： 一种在拥塞的半双工以太网网络中为站提供优先级的方法和系统。 具体地，本发明的一个实施例包括一种用于为拥塞网络中的外围组件（例如，半双工网络接口卡）提供优先级的方法。 该方法包括在耦合到网络的外围组件在数据分组传输期间检测数据分组的冲突的步骤。 此外，该方法包括确定限制退避时间的步骤。 应当理解，限制退避时间基本上等于或小于限制时间值。 此外，该方法包括在尝试通过网络重传数据分组之前使得外围组件等待受限退出时间的步骤。

公开(公告)号：US06606327B1

公开(公告)日：2003-08-12

申请号：US09371618

申请日：1999-08-10

申请人： Glen H. Lowe ,  Leslie Thorne ,  Gary Takushi

发明人： Glen H. Lowe ,  Leslie Thorne ,  Gary Takushi

IPC分类号： H04L12413

CPC分类号： H04L12/4015 ,  H04L12/413

摘要： A method to dynamically adjust the maximum back off time of an Ethernet controller in a half duplex network. Specifically, one embodiment of the present invention includes a method for providing priority to a peripheral component (e.g., half duplex Network Interface Card) in a congested network. The method includes the step of determining a maximum back off time limit based on a number of collisions a first data packet encounters before being transmitted over a network. Furthermore, the method includes the step of detecting a collision of a second data packet during transmission of the second data packet by the peripheral component coupled to the network. Additionally, the method also includes the step of determining a back off time. It should be appreciated that the back off time is substantially equal to or less than the maximum back off time limit. Moreover, the method includes the step of causing the peripheral component to wait the back off time before trying to retransmit the second data packet over the network.

摘要翻译： 一种在半双工网络中动态调整以太网控制器的最大退避时间的方法。 具体地，本发明的一个实施例包括一种用于为拥塞网络中的外围组件（例如，半双工网络接口卡）提供优先级的方法。 该方法包括基于在通过网络发送之前第一数据分组遇到的冲突的数量来确定最大退避时间限制的步骤。 此外，该方法包括在耦合到网络的外围组件在第二数据分组的传输期间检测第二数据分组的冲突的步骤。 另外，该方法还包括确定退出时间的步骤。 应当理解，退避时间基本上等于或小于最大退避时间限制。 此外，该方法包括在尝试通过网络重传第二数据分组之前使外围部件等待退出时间的步骤。

公开(公告)号：US06243785B1

公开(公告)日：2001-06-05

申请号：US09082417

申请日：1998-05-20

申请人： Glen H. Lowe ,  Claude Hayek

发明人： Glen H. Lowe ,  Claude Hayek

IPC分类号： G06F1300

CPC分类号： G06F13/24 ,  G06F2213/2406 ,  G06F2213/2408

摘要： A method and system for programmably controlling hardware generation of interrupts by a peripheral component. In one embodiment, the present invention uses a peripheral component driver to programmably define a duration for a time cycle of a hardware timer disposed on a peripheral component. The hardware timer is configured to cause the generation of an interrupt signal upon the expiration of the time cycle. In this embodiment, the hardware timer of the peripheral component implements the duration for the time cycle and causes the generation of an interrupt signal upon the expiration of the time cycle. In so doing, the present embodiment attains the reliability and consistency of hardware timer generated interrupts schemes, but, by controlling the hardware timer with software, the present embodiment prevents over utilization of the CPU by the hardware timer.

摘要翻译： 一种用于可编程地控制由外围部件产生中断的硬件的方法和系统。 在一个实施例中，本发明使用外围组件驱动器可编程地定义设置在外围组件上的硬件定时器的时间周期的持续时间。 硬件定时器被配置为在时间周期期满时产生中断信号。 在本实施例中，周边部件的硬件定时器实现时间周期的持续时间，并且在时间周期期满后产生中断信号。 这样做，本实施例达到硬件定时器产生的中断方案的可靠性和一致性，但是通过利用软件控制硬件定时器，本实施例防止硬件计时器对CPU的过度利用。