公开(公告)号：US4595911A

公开(公告)日：1986-06-17

申请号：US514208

申请日：1983-07-14

申请人： Glen R. Kregness ,  Clarence W. Dekarske ,  Peter B. Criswell

发明人： Glen R. Kregness ,  Clarence W. Dekarske ,  Peter B. Criswell

IPC分类号： G06F5/01 ,  G06F9/30 ,  G06F5/00

CPC分类号： G06F9/30025 ,  G06F5/012 ,  G06F9/30036 ,  G06F9/30167

摘要： A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting system provides field selection and justification together with the capability of complementing and magnitude generation of the selected fields. Floating-point operands in two different floating-point formats can be unpacked, that is the characteristic separated from the mantissa and properly aligned, and can be packed by positioning and recombining the characteristic with that associated mantissa. Throughout the entire reformatting process, parity for selected bit groupings is maintained, thereby allowing through checking of reformatting operations. The reformatting system includes programmably selectable constant generation.

摘要翻译： 描述了利用可编程控制的多路复用器级别的高速系统，用于将数据从可编程选择的第一格式重新格式化为第二格式。 利用交错的输入数据优化重新格式化速率。 重新格式化系统提供了现场选择和理由，以及所选领域的补充和量产能力。 可以解包两种不同浮点格式的浮点操作数，即从尾数分离的特性和正确对齐的特征，并且可以通过将特征与相关尾数进行定位和重组来进行打包。 在整个重新格式化过程中，维持所选位分组的奇偶校验，从而允许通过检查重新格式化操作。 重新格式化系统包括可编程选择的恒定生成。

公开(公告)号：US4984153A

公开(公告)日：1991-01-08

申请号：US186827

申请日：1988-04-27

申请人： Glen R. Kregness ,  Clarence W. Dekarske ,  Lawrence R. Fontaine

发明人： Glen R. Kregness ,  Clarence W. Dekarske ,  Lawrence R. Fontaine

IPC分类号： G06F15/16 ,  G06F9/46 ,  G06F9/52 ,  G06F12/00 ,  G06F15/177

CPC分类号： G06F9/52

摘要： In a plural processor data processing system, a lock is obtained on a commonly shared storage means that allows for the testing of a control word associated with a selected memory address of a particular data processor wherein each of the data processors of the system is capable of independently requesting a lock on said control word. Lock requests are broadcast to each of the data processors. The lock is then established according to predefined criteria by transmission of the lock requests of all of said processor means at the same time at controlled intervals, and by providing the lock on the control word when the requesting processor is the only processor that is requesting a given control word during a control interval, or when the processor transmits its lock request simultaneously with other processor means of a lower priority.

摘要翻译： 在多处理器数据处理系统中，在公共共享存储装置上获得锁，其允许测试与特定数据处理器的选定存储器地址相关联的控制字，其中系统的每个数据处理器能够 独立地请求锁定所述控制字。 锁定请求被广播到每个数据处理器。 然后根据预定义的标准通过以受控的间隔同时发送所有所述处理器装置的锁定请求来建立锁定，并且当请求处理器是请求处理器的唯一处理器时通过向控制字提供锁定 在控制间隔期间，或者当处理器与较低优先级的其他处理器装置同时发送其锁定请求时给定控制字。

公开(公告)号：US4930106A

公开(公告)日：1990-05-29

申请号：US237817

申请日：1988-08-29

申请人： Michael Danilenko ,  Clarence W. Dekarske ,  John E. Larson

发明人： Michael Danilenko ,  Clarence W. Dekarske ,  John E. Larson

IPC分类号： G11C8/12

CPC分类号： G11C8/12

摘要： A cache buffer for a multiprocessor system utilizes two RAMs to store validity bits. Use of these RAMs greatly reduces chip area required to implement the validity buffer and reduces interconnection foil (printed connectors) and hence propagation time. An initial clear state is written into all of the memory locations of both RAMs. One of the RAMs then becomes the active validity bit RAM and the other a standby. When a fast invalidate command is received, upon an invalidate parity error indication from a memory readout, for example, the standby RAM is switched to the active RAM, and the validity bits of the formerly active RAM are cleared in sequential write cycles after it is switched to a standby state.

摘要翻译： 用于多处理器系统的缓存缓冲器利用两个RAM来存储有效位。 这些RAM的使用大大减少了实现有效性缓冲区所需的芯片面积，并减少了互连箔（印刷连接器），从而减少了传播时间。 初始清除状态被写入两个RAM的所有存储器位置。 其中一个RAM然后变为活动有效位RAM，另一个是备用。 当接收到快速无效命令时，例如，当存储器读出中的奇偶校验错误指示无效时，备用RAM被切换到活动RAM，并且先前有效RAM的有效位在顺序写入周期之后被清除 切换到待机状态。