公开(公告)号：US20240021621A1

公开(公告)日：2024-01-18

申请号：US17812790

申请日：2022-07-15

Applicant: GlobalFoundries U.S. Inc.

Inventor： James P. Mazza ,  Xuelian Zhu ,  Jia Zeng, JR. ,  Navneet Jain ,  Mahbub Rashed

IPC: H01L27/118 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11875 ,  H01L2027/11881

Abstract: An integrated circuit (IC) structure includes a plurality of cell rows with each cell row including a plurality of (standard) cells. A power rail for at least one pair of adjacent cell rows is asymmetric relative to a cell boundary between adjacent cells of the at least one pair of adjacent cell rows. Embodiments of the disclosure can also include the standard cell including a plurality of transistors at a device layer, and at least a portion of an isolation area at an edge of the device layer defining a cell boundary. The standard cell also includes the power rail including a first portion within the cell boundary and a second portion outside the cell boundary. The first portion and the second portion have different heights such that the power rail is asymmetric across the cell boundary. The asymmetric power rail provides seamless integration of cell libraries having different heights.