公开(公告)号：US20250006842A1

公开(公告)日：2025-01-02

申请号：US18345001

申请日：2023-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Selina A. Mala ,  Pushparaj Dirgharaj Pathak ,  Chung Foong Tan

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12

Abstract: A structure includes a substrate, a first transistor on the substrate and a second transistor on the substrate. The second transistor is spaced apart from the first transistor by an isolation region. At least one stress-inducing liner is over the first transistor and the second transistor. An opening extends through at least one stress-inducing liner over at least the isolation region, and a dielectric layer is in at least a portion of the opening. The structure allows for local enhanced high-pressure deuterium (HPD) passivation, which increases threshold voltage of the transistors and improves hot carrier injection with no additional masking. A method of forming the structure is also provided.