公开(公告)号：US20250006842A1

公开(公告)日：2025-01-02

申请号：US18345001

申请日：2023-06-30

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Selina A. Mala ,  Pushparaj Dirgharaj Pathak ,  Chung Foong Tan

IPC: H01L29/78 ,  H01L21/84 ,  H01L27/12

Abstract: A structure includes a substrate, a first transistor on the substrate and a second transistor on the substrate. The second transistor is spaced apart from the first transistor by an isolation region. At least one stress-inducing liner is over the first transistor and the second transistor. An opening extends through at least one stress-inducing liner over at least the isolation region, and a dielectric layer is in at least a portion of the opening. The structure allows for local enhanced high-pressure deuterium (HPD) passivation, which increases threshold voltage of the transistors and improves hot carrier injection with no additional masking. A method of forming the structure is also provided.

公开(公告)号：US20230352348A1

公开(公告)日：2023-11-02

申请号：US17732601

申请日：2022-04-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： George R. Mulfinger ,  Md Nasir Uddin Bhuyian ,  Shesh Mani Pandey ,  Adam S. Rosenfeld ,  Selina A. Mala

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6656

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure has a semiconductor layer. A gate structure is located on the semiconductor layer. The gate structure has a sidewall spacer having a first section on the semiconductor layer and positioned laterally adjacent to the gate structure and further having a second section above and wider than the first section and positioned laterally adjacent the gate structure. A source/drain region is on the semiconductor layer and positioned laterally adjacent to the first section and the second section of the sidewall spacer.

公开(公告)号：US20250126888A1

公开(公告)日：2025-04-17

申请号：US18453507

申请日：2023-08-22

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Pushparaj Pathak ,  Selina A. Mala

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/78

Abstract: A semiconductor device includes an insulating layer, a first semiconductor layer over the insulating layer, a diffusion break structure between a first active region and a second active region and including a first insulating pattern over the insulating layer and an opening over the first insulating pattern, and a conductive gate material over the opening.

公开(公告)号：US20240188287A1

公开(公告)日：2024-06-06

申请号：US18061538

申请日：2022-12-05

Applicant: GlobalFoundries U.S. Inc.

Inventor： George Robert Mulfinger ,  Selina A. Mala ,  Shesh Mani Pandey ,  Adam S. Rosenfeld ,  Md Nasir Uddin Bhuyian

IPC: H10B20/20 ,  G11C17/16

CPC classification number: H01L27/11206 ,  G11C17/16

Abstract: A one-time programmable (OTP) fuse includes a trench isolation; a gate metal layer over the trench isolation; and a PN junction over the gate metal layer. More particularly, the OTP fuse may include a first terminal including a highly doped n-type polysilicon layer over the trench isolation, and a second terminal including a highly doped p-type polysilicon layer over the trench isolation. The highly doped n-type polysilicon layer contacts the highly doped p-type polysilicon layer, creating a PN junction and a fuse link defined in a portion of the gate metal layer between the trench isolation and the PN junction. The gate metal layer has a uniform thickness that allows better dimension control of the fuse link to reduce fuse programming current variability.