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    Voltage-controlled oscillator with tunable tail harmonic filter
    1.
    发明授权
    Voltage-controlled oscillator with tunable tail harmonic filter 有权

    公开(公告)号：US12249959B1

    公开(公告)日：2025-03-11

    申请号：US18484504

    申请日：2023-10-11

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Qiao Yang ,  Chi Zhang

    IPC: H03B5/12 ,  H03B5/04 ,  H03B5/36

    Abstract: Disclosed is a voltage-controlled oscillator (VCO) including at least an inductor-capacitor (LC) resonant circuit (including varactors that receive a variable input voltage), cross-coupled transistors connected to the LC resonant circuit, and an LC filter connected to a shared source node of the cross-coupled transistors. The cross-coupled transistors can have back gates connected to receive a variable back gate bias voltage (Vbg), which is dependent on Vin to ensure that an optimal relationship between the oscillating frequency (ω0) of the LC resonant circuit and the resonant frequency (ω1) of the LC filter is continuously maintained to minimize phase noise. For example, if Vin is increased to increase varactor capacitance and, thereby decrease ω0, then Vbg is also increased, thereby increasing the voltage (Vs-s) and the capacitance (Cs-s) on the shared source node connected to the LC filter, decreasing ω1, and maintaining an optimal relationship of ω0=ω1/2.

    STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS
    2.
    发明申请
    STATIC RANDOM ACCESS MEMORY (SRAM) CELL WITH VARIABLE TOGGLE THRESHOLD VOLTAGE AND MEMORY CIRCUIT INCLUDING SRAM CELLS 有权

    公开(公告)号：US20250078913A1

    公开(公告)日：2025-03-06

    申请号：US18459530

    申请日：2023-09-01

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Xuemei Hui ,  Shafiullah Syed ,  Qiao Yang ,  Wei Zhao

    IPC: G11C11/412 ,  G11C11/419 ,  H10B10/00

    Abstract: A static random access memory (SRAM) cell includes P-type and N-type transistors having secondary gates. A node connected to all secondary gates receives a write enable signal (WEN). A low WEN forward biases the P-type transistors and increases the toggle threshold voltage (Vtth) of the SRAM cell to avoid data switching during a read. A high WEN forward biases the N-type transistors and decreases Vtth during a write. The SRAM cell can be implemented using a fully depleted semiconductor-on-insulator technology, where the secondary gates include corresponding portions of a well region below. In this case, an array of SRAM cells can be above a single well region. Alternatively, the array can be sectioned into sub-arrays above different well regions and a decoder can output sub-array-specific WENs to the different well regions (e.g., with only one WEN being high at a given time to reduce capacitance).

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