公开(公告)号：US20240380400A1

公开(公告)日：2024-11-14

申请号：US18313427

申请日：2023-05-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Venu Gopal Reddy Ara ,  Devesh Dwivedi

IPC: H03K19/0185

Abstract: Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure of the disclosure includes a first pair of complementary transistors connected in series between a first voltage node and a second voltage node. Each transistor of the first pair includes a gate coupled to a first input node. A second pair of complementary transistors is connected in series between the first voltage node and the second voltage node in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node. An output line is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.

公开(公告)号：US20250023466A1

公开(公告)日：2025-01-16

申请号：US18350316

申请日：2023-07-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Palle Sundar Veerendranath ,  Venu Gopal Reddy Ara ,  Abdul Rajak

IPC: H02M3/07 ,  H03K19/0185

Abstract: A disclosed charge pump includes first and second stages and, optionally, additional stage(s). The first stage receives a voltage input (Vin) at a first voltage (V1), CLK1 (GND, V1), and CLK1B (V1, GND), and outputs a first stage voltage output (Vout1) at a second voltage (V2) double V1. A second stage receives Vout1, CLK2 (V1, V2), and CLK2B (V2, V1, and outputs a second stage voltage output (Vout2) at a third voltage (V3) essentially triple V1, and so on. A clock driver supplies CLK1-CLK1B to the first stage and to a clock generator. The clock generator includes: a voltage level shifter, which receives CLK1 and CLK1B and outputs multiple level-shifted voltage output pulses; and a driving circuit, which receives specific ones of the output voltage pulses and outputs CLK2 and CLK2B to the second stage and, if needed, additional voltage level-shifted clock signal-inverted clock signal pairs to any additional stages.