公开(公告)号：US20250023564A1

公开(公告)日：2025-01-16

申请号：US18350305

申请日：2023-07-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Venkatesh Periyapatna Gopinath ,  Suresh Pasupula ,  Devesh Dwivedi

IPC: H03K19/0175 ,  H03K19/00 ,  H03K19/003

Abstract: A disclosed circuit structure includes a voltage level shifter connected to a variable voltage generator for receiving a low supply voltage and to a programmable voltage generator for receiving a high supply voltage that is higher than the low supply voltage. The high supply voltage is programmable to one of multiple different voltage levels. The variable voltage generator tracks the voltage level of the high supply voltage and outputs the low supply voltage based thereon. The high supply voltage is tracked either directly or using the trim bit signal employed by the programmable voltage generator to program the high supply voltage. The low supply voltage is high when the high supply voltage is high to ensure operation within the safe operating area and is low when the high supply voltage drops below some threshold level to ensure operability and, optionally, improve operating speed.

公开(公告)号：US20250166671A1

公开(公告)日：2025-05-22

申请号：US19035131

申请日：2025-01-23

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：US12243614B2

公开(公告)日：2025-03-04

申请号：US18046961

申请日：2022-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：US20240380400A1

公开(公告)日：2024-11-14

申请号：US18313427

申请日：2023-05-08

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Venu Gopal Reddy Ara ,  Devesh Dwivedi

IPC: H03K19/0185

Abstract: Embodiments of the disclosure provide a customizable logic cells and related methods to form the same. A structure of the disclosure includes a first pair of complementary transistors connected in series between a first voltage node and a second voltage node. Each transistor of the first pair includes a gate coupled to a first input node. A second pair of complementary transistors is connected in series between the first voltage node and the second voltage node in an opposite orientation from the first pair of complementary transistors. Each transistor of the second pair includes a gate coupled to a second input node. An output line is coupled to a first electrical connection between the first pair complementary transistors and a second electrical connection between the second pair of complementary transistors.

公开(公告)号：US20240127868A1

公开(公告)日：2024-04-18

申请号：US18046961

申请日：2022-10-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi ,  Chunsung Chiang

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12

CPC classification number: G11C7/067 ,  G11C7/109 ,  G11C7/12

Abstract: Embodiments of the disclosure provide memory circuit, a sense amplifier and associated method for reading a resistive state in a memory device. The sense amplifier includes a bit cell configurable to a high or low resistance state; a sensing circuit that detects a voltage drop across the bit cell in response to an applied read current during a read operation and generates a high or low logic output at an output node; and a pulse generation circuit that increases the applied read current with an injected current pulse when a low to high transition of the resistive state of the bit cell is detected.

公开(公告)号：US12283952B2

公开(公告)日：2025-04-22

申请号：US18350327

申请日：2023-07-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Venkatesh Periyapatna Gopinath ,  Suresh Pasupula ,  Devesh Dwivedi

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/20

Abstract: A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.

公开(公告)号：US20250023566A1

公开(公告)日：2025-01-16

申请号：US18350327

申请日：2023-07-11

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Venkatesh Periyapatna Gopinath ,  Suresh Pasupula ,  Devesh Dwivedi

IPC: H03K19/0185 ,  H03K19/20

Abstract: A structure includes a level shifter, first and second variable voltage generators, and a programmable voltage generator. The level shifter includes low and high supply voltage nodes and two parallel branches, including multiple transistors, connected between the nodes. The programmable voltage generator generates and applies a high supply voltage (VH) to the high supply voltage node. VH is programmable to one of multiple possible VH levels. Based on the voltage level of VH, the first variable voltage generator generates and applies a low supply voltage (VL) to the low supply voltage node and the second variable voltage generator generates and applies a gate bias voltage (VGB) to gates of some transistors. By tracking VH and adjusting VL and VGB based on thereon, the voltage level shifter operates within the SOA at high VHs, remains operable at low VHs, and maintains operating speed at mid-level VHs.

公开(公告)号：US20240282373A1

公开(公告)日：2024-08-22

申请号：US18170925

申请日：2023-02-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Suresh Pasupula ,  Devesh Dwivedi

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/004 ,  G11C11/1673 ,  G11C2013/0054

Abstract: Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2˜½*VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.

公开(公告)号：US11705891B1

公开(公告)日：2023-07-18

申请号：US17663671

申请日：2022-05-17

Applicant: GlobalFoundries U.S. Inc.

Inventor： Siva Kumar Chinthu ,  Devesh Dwivedi ,  Sundar Veerendranath Palle ,  Lejan Pu

IPC: H03K19/0175 ,  H03K3/012 ,  H03K3/356 ,  G11C7/10 ,  H03K19/0185

CPC classification number: H03K3/012 ,  G11C7/1051 ,  G11C7/1078 ,  H03K3/356113 ,  H03K19/0185 ,  H03K19/017509

Abstract: Embodiments of the present disclosure provide a level shifter, including: first and second NMOS transistors, wherein the sources of the first and second NMOS transistors are coupled to a first voltage, the gate of the first NMOS transistor is connected to an inverse of an input signal that varies between a second voltage and a third voltage, and wherein the gate of the second NMOS transistor receives a buffer of the input signal. a breakdown protection circuit has third and fourth NMOS transistors, the gates of the third and fourth NMOS transistors being connected to the third voltage, the drain of the first NMOS transistor being connected to the source of the third NMOS transistor, and the drain of the second NMOS transistor being connected to the source of the fourth NMOS transistor. A pull-up circuit is connected to the drains of the third and fourth NMOS transistors.