公开(公告)号：US09876019B1

公开(公告)日：2018-01-23

申请号：US15209102

申请日：2016-07-13

申请人： Globalfoundries Singapore Pte. Ltd.

发明人： Xiong Zhang ,  Sunny Sadana ,  Yudi Setiawan ,  Yoke Leng Lim ,  Siow Lee Chwa

IPC分类号： H01L21/02 ,  H01L27/11521 ,  H01L21/762 ,  H01L29/06 ,  H01L21/28 ,  H01L21/311 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L29/42328 ,  H01L29/66825

摘要： Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.

公开(公告)号：US20180019249A1

公开(公告)日：2018-01-18

申请号：US15209102

申请日：2016-07-13

申请人： Globalfoundries Singapore Pte. Ltd.

发明人： Xiong Zhang ,  Sunny Sadana ,  Yudi Setiawan ,  Yoke Leng Lim ,  Siow Lee Chwa

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/66 ,  H01L29/06

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L21/76224 ,  H01L29/42328 ,  H01L29/66825

摘要： Methods of producing integrated circuits and integrated circuits produced by those methods are provided. In an exemplary embodiment, a method of producing an integrated circuit includes forming first and second shallow trench isolations within a substrate, where the first and second shallow trench isolations have an initial shallow trench height. A base well is formed in the substrate, where the base well is positioned between the first and second shallow trench isolations. A gate dielectric is formed overlying the base well, and a floating gate is formed overlying the gate dielectric. An initial shallow trench height is reduced to a reduced shallow trench height shorter than the initial shallow trench height after the floating gate is formed.