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公开(公告)号:US20170373823A1
公开(公告)日:2017-12-28
申请号:US15649078
申请日:2017-07-13
Applicant: Google Inc.
Inventor: Leon Zhou , Sheng-Hui Yang
CPC classification number: H04L7/0075 , H04B10/11 , H04L7/0016 , H04L7/0029 , H04L7/0083 , H04L7/033 , H04L7/0331 , H04L7/10
Abstract: A method includes receiving an optical signal through an optical link and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving power threshold and transitioning a clock and data recovery circuit form a normal mode to a holdover mode when the receiving power is less than the first receiving power threshold. The clock and data recovery circuit, when operating in the holdover mode, configured to hold a recovered clock to a known-good clock frequency. When the receiving power for the optical link is greater than a second receiving power threshold, the method initiates a transition of the clock and data recovery circuit from the holdover mode to the normal mode and reacquires synchronization between the recovered clock and a current rate of the incoming data stream using the known-good clock frequency.
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公开(公告)号:US09749123B1
公开(公告)日:2017-08-29
申请号:US15176984
申请日:2016-06-08
Applicant: Google Inc.
Inventor: Leon Zhou , Sheng-Hui Yang
CPC classification number: H04L7/0075 , H04B10/11 , H04L7/0016 , H04L7/0029 , H04L7/0083 , H04L7/033 , H04L7/0331 , H04L7/10
Abstract: A method includes receiving an optical signal through an optical link and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving power threshold and transitioning a clock and data recovery circuit form a normal mode to a holdover mode when the receiving power is less than the first receiving power threshold. The clock and data recovery circuit, when operating in the holdover mode, configured to hold a recovered clock to a known-good clock frequency. When the receiving power for the optical link is greater than a second receiving power threshold, the method initiates a transition of the clock and data recovery circuit from the holdover mode to the normal mode and reacquires synchronization between the recovered clock and a current rate of the incoming data stream using the known-good clock frequency.
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