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公开(公告)号：US11250537B2
公开(公告)日：2022-02-15
申请号：US16694335
申请日：2019-11-25
Applicant: Google LLC
Inventor： Fabrizio Basso , Edward Chang , Daniel Finchelstein , Timothy Knight , William Mark , Albert Meixner , Shahriar Rabii , Jason Redgrave , Masumi Reynders , Ofer Shacham , Don Stark , Michelle Tomasko
Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.
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Patent Agency Ranking
公开(公告)号：US20200167890A1
公开(公告)日：2020-05-28
申请号：US16694335
申请日：2019-11-25
Applicant: Google LLC
Inventor： Fabrizio Basso , Edward Chang , Daniel Finchelstein , Timothy Knight , William Mark , Albert Meixner , Shahriar Rabii , Jason Redgrave , Masumi Reynders , Ofer Shacham , Don Stark , Michelle Tomasko
Abstract: An image processor unit is described. The image processor unit includes a plurality of inputs to receive at least one input image. The image processor unit includes a plurality of outputs to provide at least one output image. The image processor unit includes a network coupled to the plurality of inputs and the plurality of outputs. The network is to couple at least one of the inputs to at least one of the outputs. The image processor unit includes an image processor circuit coupled to the network. The network to route an input image that is received at one of the inputs to the image processor circuit. The image processor circuit is to execute image signal processing program code to generate a processed output image from the input image. The network is to route the processed output image to at least one of the outputs.
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公开(公告)号：US10481870B2
公开(公告)日：2019-11-19
申请号：US15594223
申请日：2017-05-12
Applicant: Google LLC
Inventor： Artem Vasilyev , Albert Meixner , Jason Redgrave
Abstract: An execution unit is described. The execution unit includes an arithmetic logic unit (ALU) circuit having a first input to receive a first value and a second input to receive a second value. The ALU circuit includes circuitry to determine an absolute value of the first value and to add the absolute value to the second value. The first input is coupled to a first data path having register space and an output of another ALU of the execution unit circuit as alternative sources of the first value. The second input is coupled to a second data path having the register space as a source for the second value.
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公开(公告)号：US10789202B2
公开(公告)日：2020-09-29
申请号：US15594502
申请日：2017-05-12
Applicant: Google LLC
Inventor： Jason Redgrave , Albert Meixner , Ji Kim , Ofer Shacham
IPC: G06F15/80 , G06T1/20 , G06F15/173 , G06F1/3234
Abstract: A method is described. The method includes configuring a first instance of object code to execute on a processor. The processor has multiple cores and an internal network. The internal network is configured in a first configuration that enables a first number of the cores to be communicatively coupled. The method also includes configuring a second instance of the object code to execute on a second instance of the processor. A respective internal network of the second instance of the processor is configured in a second configuration that enables a different number of cores to be communicatively coupled, wherein, same positioned cores on the processor and the second instance of the processor have same network addresses for the first and second configurations. A processor is also described having an internal network designed to enable the above method.
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公开(公告)号：US10706006B2
公开(公告)日：2020-07-07
申请号：US16547487
申请日：2019-08-21
Applicant: Google LLC
Inventor： Asif Khan , Jason Redgrave , Neeti Desai , David Warren
Abstract: An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.
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公开(公告)号：US20190377705A1
公开(公告)日：2019-12-12
申请号：US16547487
申请日：2019-08-21
Applicant: Google LLC
Inventor： Asif Khan , Jason Redgrave , Neeti Desai , David Warren
Abstract: An image processor is described. The image processor includes a storage circuit to store segments of input image data received in a raster scan format. The image processor further includes a reformatting circuit to convert the segments of input image data into a block image format. The image processor further includes a processor comprising a two-dimensional execution lane array and a two-dimensional shift register array. The two-dimensional shift register array is to store the input image data that has been formatted into the block image format. The execution lane array is to execute instructions that operate on the image data from the two-dimensional shift register array.
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