公开(公告)号：US20240296102A1

公开(公告)日：2024-09-05

申请号：US18116075

申请日：2023-03-01

Applicant: Google LLC

Inventor： Ori Isachar ,  Shay Gal-On ,  Martin Guy Dixon

IPC: G06F11/26 ,  G06F11/22

CPC classification number: G06F11/26 ,  G06F11/2242

Abstract: The technology generally relates to systems and methods for performing in-field testing of processing cores within a system-on-chip (SoC), so as to identify faults, including those associated with silent data corruption. For example, an SoC may contain operational cores and spare cores. An operational core may be selected for testing while a spare core is used to replace the tested core. In addition, a spare core may be used to replace an operational core that has been determined to be corrupted.

公开(公告)号：US20240231667A1

公开(公告)日：2024-07-11

申请号：US18152428

申请日：2023-01-10

Applicant: Google LLC

Inventor： Sheng Li ,  Sridhar Lakshmanamurthy ,  Norman Paul Jouppi ,  Martin Guy Dixon ,  Daniel Stodolsky ,  Quoc V. Le ,  Liqun Cheng ,  Erik Karl Norden ,  Parthasarathy Ranganathan

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0611 ,  G06F3/067

Abstract: Aspects of the disclosure are directed to a heterogeneous machine learning accelerator system with compute and memory nodes connected by high speed chip-to-chip interconnects. While existing remote/disaggregated memory may require memory expansion via remote processing units, aspects of the disclosure add memory nodes into machine learning accelerator clusters via the chip-to-chip interconnects without needing assistance from remote processing units to achieve higher performance, simpler software stack, and/or lower cost. The memory nodes may support prefetch and intelligent compression to enable the use of low cost memory without performance degradation.