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公开(公告)号：US12056534B2
公开(公告)日：2024-08-06
申请号：US18091951
申请日：2022-12-30
Applicant: Google LLC
Inventor： Sheng Li , Brian Zhang , Liqun Cheng , Norman Paul Jouppi , Yun Ni
CPC classification number: G06F9/5044 , G06F9/4881 , G06F9/5011 , G06F9/5066 , G06F9/545 , G06F11/3409 , G06F11/3612 , G06F18/214 , G06N3/08 , G06F2209/501
Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scheduling operations represented as a computational graph on a distributed computing network. A method includes: receiving data representing operations to be executed in order to perform a job on a plurality of hardware accelerators of a plurality of different accelerator types; generating, for the job and from at least the data representing the operations, features that represent a predicted performance for the job on hardware accelerators of the plurality of different accelerator types; generating, from the features, a respective predicted performance metric for the job for each of the plurality of different accelerator types according to a performance objective function; and providing, to a scheduling system, one or more recommendations for scheduling the job on one or more recommended types of hardware accelerators.
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公开(公告)号：US12026118B2
公开(公告)日：2024-07-02
申请号：US17537366
申请日：2021-11-29
Applicant: Google LLC
Inventor： Nishant Patil , Liqun Cheng
CPC classification number: G06F13/4226 , G06F13/4018
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.
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公开(公告)号：US10908964B2
公开(公告)日：2021-02-02
申请号：US16198583
申请日：2018-11-21
Applicant: Google LLC
Inventor： Liqun Cheng , Rama Krishna Govindaraju , Haishan Zhu , David Lo , Parthasarathy Ranganathan , Nishant Patil
Abstract: Methods, systems, and computer storage media storing instructions for managing processing system efficiency. One of the methods includes obtaining data splitting a plurality of general-purpose processing units in a processing system into a high-priority domain and a low-priority domain, wherein the general-purpose processing units in the high-priority domain are assigned to perform one or more tasks comprising one or more high-priority tasks, and the general-purpose processing units in the low-priority domain are assigned to perform one or more low-priority tasks; and during runtime of the processing system, obtaining memory usage measurements that characterize usage of system memory by the high-priority domain and the low-priority domain; and adjusting, based on the memory usage measurements, a configuration of (i) the high-priority domain, (ii) the low-priority domain, or (iii) both to adjust utilization of the system memory by the general-purpose processing units.
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公开(公告)号：US10216636B2
公开(公告)日：2019-02-26
申请号：US16046396
申请日：2018-07-26
Applicant: Google LLC
Inventor： Rama Krishna Govindaraju , Liqun Cheng , Parthasarathy Ranganathan
IPC: G06F12/00 , G06F12/0862 , G06F3/06 , G06F12/0868
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for pre-fetching data. The methods, systems, and apparatus include actions of providing a request for data to an input-output device and receiving a set of memory addresses for the requested data. Additional actions include determining a subset of the memory addresses, providing a request for a processor to pre-fetch or inject data corresponding to the subset of the memory addresses, and receiving the requested data and the set of memory addresses. Additional actions include determining that the received data includes data for the subset of memory addresses that has been requested to be pre-fetched or injected, storing the data for the subset of memory addresses in a cache of the processor, and storing remaining data of the received data for the memory addresses in a main memory.
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5.发明公开公开(公告)号：US20230297580A1
公开(公告)日：2023-09-21
申请号：US17721873
申请日：2022-04-15
Applicant: Google LLC
Inventor： Sheng Li , Garrett Axel Andersen , Norman Paul Jouppi , Quoc V. Le , Liqun Cheng , Parthasarathy Ranganathan , Julian Paul Grady , Yang Li , Martin Wicke , Yifeng Lu , Yun Ni , Kun Wang
IPC: G06F16/2457 , G06F16/2455 , G06N3/063
CPC classification number: G06F16/2457 , G06F16/24554 , G06N3/063
Abstract: According to various implementations, generally disclosed herein is a hybrid and hierarchical neural architecture search (NAS) approach. The approach includes performing a search space partitioning scheme to divide the search space into sub-search spaces. The approach further includes performing a first type of NAS, such as a Multi-trial NAS, to cover a search across the sub-search spaces. The approach also includes performing a second type of NAS, such as a One-Shot NAS, to cover each sub-search space. The approach further includes automatically stopping the second type of NAS based on one or more early stopping criteria.
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Patent Agency Ranking
公开(公告)号：US20230222000A1
公开(公告)日：2023-07-13
申请号：US18091951
申请日：2022-12-30
Applicant: Google LLC
Inventor： Sheng Li , Brian Zhang , Liqun Cheng , Norman Paul Jouppi , Yun Ni
CPC classification number: G06F9/5044 , G06F9/545 , G06F11/3612 , G06F9/5066 , G06F18/214 , G06N3/08 , G06F9/5011 , G06F11/3409 , G06F9/4881 , G06F2209/501
Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for scheduling operations represented as a computational graph on a distributed computing network. A method includes: receiving data representing operations to be executed in order to perform a job on a plurality of hardware accelerators of a plurality of different accelerator types; generating, for the job and from at least the data representing the operations, features that represent a predicted performance for the job on hardware accelerators of the plurality of different accelerator types; generating, from the features, a respective predicted performance metric for the job for each of the plurality of different accelerator types according to a performance objective function; and providing, to a scheduling system, one or more recommendations for scheduling the job on one or more recommended types of hardware accelerators.
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公开(公告)号：US20220229698A1
公开(公告)日：2022-07-21
申请号：US17150285
申请日：2021-01-15
Applicant: Google LLC
Inventor： David Lo , Liqun Cheng , Parthasarathy Ranganathan , Sundar Jayakumar Dev
Abstract: The subject matter described herein provides systems and techniques to address the challenges of growing hardware and workload heterogeneity using a Warehouse-Scale Computer (WSC) design that improves the efficiency and utilization of WSCs. The WSC design may include an abstraction layer and an efficiency layer in the software stack of the WSC. The abstraction layer and the efficiency layer may be designed to improve job scheduling, simplify resource management, and drive hardware-software co-optimization using machine learning techniques and automation in order to customize the WSC for applications at scale. The abstraction layer may embrace platform/hardware and workload diversity through greater coordination between hardware and higher layers of the WSC software stack in the WSC design. The efficiency layer may employ machine learning techniques at scale to realize hardware/software co-optimizations as a part of the autonomous WSC design.
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公开(公告)号：US20200371984A1
公开(公告)日：2020-11-26
申请号：US16524964
申请日：2019-07-29
Applicant: Google LLC
Inventor： Nishant Patil , Liqun Cheng
Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, are described for performing asymmetric data communication at a host-device interface of a system. The methods include identifying devices coupled to a host of the system and generating a system topology that identifies a connectivity of the devices and identifies bus lanes that enable data transfers at the system. The host determines that a first connection between the host and a first device of the multiple devices has an asymmetric bandwidth requirement. The host configures a set of bus lanes of a data bus connecting the first device and the host to allocate a different number of the bus lanes to data egress from the host than to data ingress to the host. The bus lanes are configured to allocate the differing number of bus lanes based on the asymmetric bandwidth requirement of the first connection.
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公开(公告)号：US20190236010A1
公开(公告)日：2019-08-01
申请号：US16379303
申请日：2019-04-09
Applicant: Google LLC
Inventor： Richard Yoo , Liqun Cheng , Benjamin C. Serebrin , Parthasarathy Ranganathan , Rama Krishna Govindaraju
IPC: G06F12/0811 , G06F9/4401 , G06F1/3234 , G06F12/0897 , G06F12/0871
CPC classification number: G06F12/0811 , G06F1/3275 , G06F9/4401 , G06F12/0871 , G06F12/0897 , G06F2212/283
Abstract: Methods, systems, and apparatus, including computer programs encoded on computer storage media, for caching data not frequently accessed. One of the methods includes receiving a request for data from a component of a device, determining that the data satisfies an infrequency condition, in response to determining that the data satisfies the infrequency condition: determining a target cache level which defines a cache level within a cache level hierarchy of a particular cache at which to store infrequently accessed data, the target cache level being lower than a highest cache level in the cache level hierarchy, requesting and receiving the data from a memory that is not a cache of the device, and storing the data in a level of the particular cache that is at or below the target cache level in the cache level hierarchy, and providing the data to the component.
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公开(公告)号：US10191672B2
公开(公告)日：2019-01-29
申请号：US14885786
申请日：2015-10-16
Applicant: Google LLC
Inventor： Rama Krishna Govindaraju , Liqun Cheng , Parthasarathy Ranganathan , Michael R. Marty , Andrew Gallatin
IPC: G06F3/06 , G06F12/1081 , G06F12/0888
Abstract: An example method includes during execution of a software application by a processor, receiving, by a copy processor separate from the processor, a request for an asynchronous data copy operation to copy data within a memory accessible by the copy processor, wherein the request is received from a copy manager accessible by the software application in a user space of an operating system managing execution of the software application; in response to the request, initiating, by the copy processor, the asynchronous data copy operation; continuing execution of the software application by the processor; determining, by the copy processor, that the asynchronous data copy operation has completed; and in response to determining that the asynchronous copy operation has completed, selectively notifying, by the copy processor, the software application that the asynchronous copy operation has completed.
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