摘要:
System and method for creating a graphical program that uses multiple models of computation (MoC). A first plurality of graphical program elements is assembled in a graphical program in response to first input, where the assembled first plurality of graphical program elements have a first MoC. A structure is displayed in the graphical program indicating use of a second MoC for graphical program elements comprised within the interior of the structure. A second plurality of graphical program elements is assembled within the structure in response to second input, where the assembled second plurality of graphical program elements have the second MoC. The graphical program is executable to perform a function, for example, by executing the assembled first plurality of graphical program elements in accordance with the first model of computation, and executing the assembled second plurality of graphical program elements in accordance with the second model of computation.
摘要:
System and method for creating and executing a graphical program. A first plurality of graphical program elements (GPEs) having a first model of computation (MoC), e.g., homogenous dataflow, are assembled in a graphical program in response to first input. A structure, including an interior portion, is displayed in the graphical program, indicating use of a second MoC, e.g., multi-rate dataflow, for GPEs within the interior portion. A second plurality of GPEs having the second MoC are assembled within the interior portion of the structure in response to second input. The second plurality of GPEs are converted into a new third plurality of GPEs having the first MoC, e.g., by parsing the second plurality of GPEs to determine multiple primitives according to the second MoC, determining the third plurality of GPEs based on the primitives, and assembling the third plurality of GPEs in the graphical program.
摘要:
A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.
摘要:
A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.
摘要:
A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
摘要:
A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.
摘要:
A computer-implemented system and method for generating a hardware implementation of graphical code. The method comprises first creating a graphical program. A first portion of the graphical program may optionally be compiled into machine code for execution by a CPU. A second portion of the graphical program is converted into a hardware implementation according to the present invention. The operation of converting the graphical program into a hardware implementation comprises exporting the second portion of the graphical program into a hardware description, wherein the hardware description describes a hardware implementation of the second portion of the graphical program, and then configuring a programmable hardware element utilizing the hardware description to produce a configured hardware element. The configured hardware element thus implements a hardware implementation of the second portion of the graphical program.
摘要:
A computer-implemented system and method for deploying a graphical program onto an image acquisition (IMAQ) device. The method may operate to configure an image acquisition (IMAQ) device to perform image processing or machine vision functions, wherein the device includes a programmable hardware element and/or a processor and memory. The method comprises first creating a graphical program which implements the image processing or machine vision function. A portion of the graphical program may be converted into a hardware implementation on a programmable hardware element, and a portion may optionally be compiled into machine code for execution by a CPU. The programmable hardware element is thus configured utilizing a hardware description and implements a hardware implementation of at least a portion of the graphical program. The CPU-executable code may be executed by a computer coupled to the IMAQ device, or by a processor/memory on the IMAQ device.
摘要:
A system and method for specifying timing relationships among nodes in a graphical program. User input specifying desired timing of a first node with respect to timing of a second node may be received. In various embodiments, any kind of timing relationship or timing constraint between the first node and the second node may be specified. Timing information may be displayed on the display to visually indicate the timing of the first node with respect to timing of the second node. In one embodiment, displaying the timing information may comprise displaying a timing wire between the first node and the second node. The graphical program may be executed in such a way that the visually indicated timing of the first node with respect to timing of the second node is satisfied.
摘要:
A system and method for automatically generating a data flow diagram in response to a first diagram. The first diagram may specify one or more states and one or more state transitions, wherein each state transition specifies a transition from a first state to a second state. A data flow diagram may be automatically generated from the first diagram. A hardware description may be generated from the data flow diagram. The hardware description may be usable to configure a programmable hardware element such as, for example, a field-programmable gate array (FPGA). The configured programmable hardware element may implement a hardware implementation of the data flow diagram.