公开(公告)号：US07057433B2

公开(公告)日：2006-06-06

申请号：US10774933

申请日：2004-02-09

申请人： Guen-Hee Cho ,  Kyu-Hyoun Kim

发明人： Guen-Hee Cho ,  Kyu-Hyoun Kim

IPC分类号： H03L7/00

CPC分类号： H03L7/0814

摘要： A delay-locked loop (DLL) capable of directly receiving external clock signals is provided. The DLL comprises a level selector, a control signal generator, and an internal clock signal generator. The level selector receives an external clock signal, and directly outputs the external clock signal, or changes a level of the external clock signal and outputs a changed external clock signal, in response to a control signal. The control signal generator generates the control signal. The internal clock signal generator receives an output signal of the level selector and the external clock signal, and generates an internal clock signal synchronized to a phase of an output signal of the level selector.

摘要翻译： 提供能够直接接收外部时钟信号的延迟锁定环（DLL）。 DLL包括电平选择器，控制信号发生器和内部时钟信号发生器。 电平选择器接收外部时钟信号，并且响应于控制信号直接输出外部时钟信号，或改变外部时钟信号的电平并输出改变的外部时钟信号。 控制信号发生器产生控制信号。 内部时钟信号发生器接收电平选择器和外部时钟信号的输出信号，并且产生与电平选择器的输出信号的相位同步的内部时钟信号。