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    Delay-Locked Loop (DLL) capable of directly receiving external clock signals
    1.
    发明授权
    Delay-Locked Loop (DLL) capable of directly receiving external clock signals 失效
    能够直接接收外部时钟信号的延迟锁定环（DLL）

    公开(公告)号：US07057433B2

    公开(公告)日：2006-06-06

    申请号：US10774933

    申请日：2004-02-09

    申请人： Guen-Hee Cho ,  Kyu-Hyoun Kim

    发明人： Guen-Hee Cho ,  Kyu-Hyoun Kim

    IPC分类号： H03L7/00

    CPC分类号： H03L7/0814

    摘要： A delay-locked loop (DLL) capable of directly receiving external clock signals is provided. The DLL comprises a level selector, a control signal generator, and an internal clock signal generator. The level selector receives an external clock signal, and directly outputs the external clock signal, or changes a level of the external clock signal and outputs a changed external clock signal, in response to a control signal. The control signal generator generates the control signal. The internal clock signal generator receives an output signal of the level selector and the external clock signal, and generates an internal clock signal synchronized to a phase of an output signal of the level selector.

    摘要翻译： 提供能够直接接收外部时钟信号的延迟锁定环（DLL）。 DLL包括电平选择器，控制信号发生器和内部时钟信号发生器。 电平选择器接收外部时钟信号，并且响应于控制信号直接输出外部时钟信号，或改变外部时钟信号的电平并输出改变的外部时钟信号。 控制信号发生器产生控制信号。 内部时钟信号发生器接收电平选择器和外部时钟信号的输出信号，并且产生与电平选择器的输出信号的相位同步的内部时钟信号。

    Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same
    2.
    发明授权
    Integrated circuit die stacks having initially identical dies personalized with fuses and methods of manufacturing the same 有权
    集成电路芯片堆叠具有最初相同的裸片，其具有熔丝和其制造方法

    公开(公告)号：US09076770B2

    公开(公告)日：2015-07-07

    申请号：US13569267

    申请日：2012-08-08

    申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

    IPC分类号： H01L23/48 ,  H01L23/525 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18

    CPC分类号： H01L23/481 ,  H01L23/5256 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

    摘要： Integrated circuit die stacks having a first die mounted upon a substrate, the first die manufactured to be initially identical to a second die with a plurality of through silicon vias (‘TSVs’), the first die personalized by blowing fuses on the first die, converting the TSVs previously connected through the blown fuses into pass-through vias (‘PTVs’), each PTV implementing a conductive pathway through the first die with no connection to any circuitry on the first die; and the second die, manufactured to be initially identical to the first die and later personalized by blowing fuses on the second die, the second die mounted upon the first die so that the PTVs in the first die connect signal lines from the substrate through the first die to TSVs in the second die.

    摘要翻译： 具有安装在基板上的第一管芯的集成电路管芯堆叠，所述第一管芯被制造成与具有多个穿通硅通孔（“TSV”）的第二管芯初始相同，所述第一管芯通过在第一管芯上吹入保险丝来个性化， 将先前通过熔断保险丝连接的TSV转换成通过通孔（“PTV”），每个PTV通过第一管芯实现导电通路，而不连接到第一管芯上的任何电路; 以及第二模具，其被制造为与第一模具初始相同，然后通过在第二模具上吹入熔丝而进行个性化，第二模具安装在第一模具上，使得第一模具中的PTV将来自基板的信号线连接到第一模具 在第二次死亡时死于TSV。

    Method of detecting error in a semiconductor memory device
    3.
    发明授权
    Method of detecting error in a semiconductor memory device 有权
    检测半导体存储器件中的误差的方法

    公开(公告)号：US08756475B2

    公开(公告)日：2014-06-17

    申请号：US12929250

    申请日：2011-01-11

    申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

    IPC分类号： H03M13/00 ,  H03M13/29 ,  G06F11/08

    CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

    摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

    摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

    Jitter suppressing delay locked loop circuits and related methods
    4.
    发明授权
    Jitter suppressing delay locked loop circuits and related methods 失效
    抖动抑制延迟锁定环路电路及相关方法

    公开(公告)号：US07212052B2

    公开(公告)日：2007-05-01

    申请号：US10925522

    申请日：2004-08-25

    申请人： Kyu-Hyoun Kim

    发明人： Kyu-Hyoun Kim

    IPC分类号： H03L7/06

    CPC分类号： H03L7/0812

    摘要： Delay locked loop circuits are provided that include a delay locked loop that generates a delay locked loop output signal and a jitter suppressor. The jitter suppressor may comprise a delay circuit that receives the delay locked loop output signal and generates one or more delayed versions of the delay locked loop output signal and a phase interpolator that receives the delay locked loop output signal and the one or more delayed versions of the delay locked loop output signal. In certain embodiments of the present invention, the delay circuit may comprise a plurality of serially connected delay cells. Each of these delay cells may delay signals input thereto for at time equal to one clock period of an external clock signal that is input to the delay locked loop.

    摘要翻译： 提供延迟锁定环路电路，其包括产生延迟锁定环路输出信号的延迟锁定环路和抖动抑制器。 抖动抑制器可以包括延迟电路，其接收延迟锁定环路输出信号并产生延迟锁定环路输出信号的一个或多个延迟版本;以及相位插值器，其接收延迟锁定环路输出信号和一个或多个延迟锁定环路输出信号 延迟锁定环路输出信号。 在本发明的某些实施例中，延迟电路可以包括多个串联连接的延迟单元。 这些延迟单元中的每一个可以在等于输入到延迟锁定环路的外部时钟信号的一个时钟周期的时间延迟输入的信号。

    Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals
    5.
    发明申请
    Duty cycle correction circuits suitable for use in delay-locked loops and methods of correcting duty cycles of periodic signals 失效
    适用于延迟锁定环路的占空比校正电路以及校正周期信号占空比的方法

    公开(公告)号：US20050122149A1

    公开(公告)日：2005-06-09

    申请号：US11005821

    申请日：2004-12-07

    申请人： Geun-Hee Cho ,  Kyu-Hyoun Kim

    发明人： Geun-Hee Cho ,  Kyu-Hyoun Kim

    IPC分类号： G11C8/00 ,  H03K5/04 ,  H03K5/135 ,  H03K5/151 ,  H03K5/156 ,  H03L7/081

    CPC分类号： H03K5/151 ,  H03K5/135 ,  H03K5/1565 ,  H03L7/0812

    摘要： Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.

    摘要翻译： 延迟锁定环集成电路包括占空比校正电路。 该占空比校正电路响应于具有不均匀占空比的至少一个输入时钟信号而产生具有基本均匀的占空比的至少一个输出时钟信号。 占空比校正电路还响应于在占空比校正电路内同步省电占空比更新操作的定时的待机控制信号。 这些更新操作重置校正电路的设定点。

    Semiconductor memory device post-repair circuit and method
    7.
    发明授权
    Semiconductor memory device post-repair circuit and method 有权
    半导体存储器件修复后电路及方法

    公开(公告)号：US06704228B2

    公开(公告)日：2004-03-09

    申请号：US10160703

    申请日：2002-05-30

    申请人： Seong-Jin Jang ,  Kyu-Hyoun Kim

    发明人： Seong-Jin Jang ,  Kyu-Hyoun Kim

    IPC分类号： G11C2900

    CPC分类号： G11C29/785

    摘要： The ability to repair defective cells in a memory array, by replacing those cells with redundant cells, is improved using a redundant memory line control circuit that employs two types of redundancy programming. Most, or all, redundant memory lines can be programmed while the memory array is in a wafer state by, e.g., cutting laser fuses. But at least one memory line can be programmed subsequent to device packaging (“post repair”) using, e.g., commands that cut electric fuses. Preferably, the redundant memory line(s) that are reserved for post repair are selectable among the same redundant memory lines that can be programmed using laser fuses. This allows all redundant memory lines to be available for laser repair, if needed, but also allows a redundant memory line to be selected for post repair after it has been determined that that redundant memory line is defect-free. This increases the likelihood that a device will be repairable, and yet does not unnecessarily waste redundant memory lines by pre-dedicating them to laser or post repair.

    摘要翻译： 使用采用两种类型的冗余编程的冗余存储器线路控制电路来改进通过用冗余单元替换这些单元来修复存储器阵列中的有缺陷的单元的能力。 当存储器阵列通过例如切割激光熔丝处于晶片状态时，大多数或全部冗余存储器线可被编程。 但是，在使用例如切断电保险丝的命令之后，可以在器件封装（“后修复”）之后至少编写一条存储器线。 优选地，可以在可以使用激光熔丝编程的相同冗余存储器线中选择用于后修复的冗余存储器线。 这样，如果需要，所有冗余存储器线路都可用于激光修复，同时也可以在确定冗余存储器线路无缺陷之后，选择冗余存储器线进行后期修复。 这增加了设备可修复的可能性，并且不会通过预先将其专用于激光或后修复而不必要地浪费冗余的存储器线。