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1.发明申请FACILITATING DATA COHERENCY USING IN-MEMORY TAG BITS AND TAG TEST INSTRUCTIONS 失效使用内存标签位置和标签测试指令来提高数据密码公开(公告)号：US20120296877A1
公开(公告)日：2012-11-22
申请号：US13109254
申请日：2011-05-17
IPC分类号： G06F17/30
CPC分类号： G06F9/30076 , G06F12/0815 , G06F12/0875 , G06F12/1027 , G06F12/1425 , G06F21/79 , G06F2212/452
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.
摘要翻译： 通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供对原始数据的数据修改的细粒度检测。 保护位指示存储在相关联的粒子中的原始数据是否受到数据一致性的保护。 保护位通过专用指令进行设置和清除。 响应于尝试访问从原始数据获得的翻译数据，检查与原始数据相关联的保护位，以确定保护位是否不能指示原始数据的一致性，如果是，则丢弃 启动翻译的数据以便于维持原始数据和翻译数据之间的数据一致性。
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2.发明申请公开(公告)号：US20120297109A1
公开(公告)日：2012-11-22
申请号：US13109249
申请日：2011-05-17
IPC分类号： G06F12/08
CPC分类号： G06F12/145 , G06F9/4552 , G06F12/1045 , G06F2212/1008
摘要： Fine-grained detection of data modification of original data is provided by associating separate guard bits with granules of memory storing the original data from which translated data has been obtained. The guard bits facilitate indicating whether the original data stored in the associated granule is indicated as protected. The guard bits are set and cleared by special-purpose instructions. Responsive to initiating a data store operation to modify the original data, the associated guard bit(s) are checked to determine whether the original data is indicated as protected. Responsive to the checking indicating that a guard bit is set for the associated original data, the data store operation to modify the original data is faulted and the translated data is discarded, thereby facilitating data coherency between the original data and the translated data.
摘要翻译： 通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联来提供原始数据的数据修改的细粒度检测。 保护位有助于指示存储在相关联的颗粒中的原始数据是否被指示为受保护的。 保护位通过专用指令进行设置和清除。 响应于启动数据存储操作以修改原始数据，检查相关联的保护位以确定原始数据是否被指示为受保护的。 响应于指示为相关联的原始数据设置了保护位的检查，修改原始数据的数据存储操作发生故障，并且转换的数据被丢弃，从而促进原始数据和转换的数据之间的数据一致性。
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3.发明申请FACILITATING DATA COHERENCY USING IN-MEMORY TAG BITS AND TAG TEST INSTRUCTIONS 失效使用内存标签位置和标签测试指令来提高数据密码公开(公告)号：US20120297146A1
公开(公告)日：2012-11-22
申请号：US13451682
申请日：2012-04-20
CPC分类号： G06F9/30076 , G06F12/0815 , G06F12/0875 , G06F12/1027 , G06F12/1425 , G06F21/79 , G06F2212/452
摘要： A method is provided for fine-grained detection of data modification of original data by associating separate guard bits with granules of memory storing original data from which translated data has been obtained. The guard bits indicating whether the original data stored in the associated granule is protected for data coherency. The guard bits are set and cleared by special-purpose instructions. Responsive to attempting access to translated data obtained from the original data, the guard bit(s) associated with the original data is checked to determine whether the guard bit(s) fail to indicate coherency of the original data, and if so, discarding of the translated data is initiated to facilitate maintaining data coherency between the original data and the translated data.
摘要翻译： 提供了一种通过将单独的保护位与存储已经获得翻译数据的原始数据的存储器的颗粒相关联的方法来对原始数据的数据修改进行细粒度检测。 保护位指示存储在相关联的粒子中的原始数据是否受到数据一致性的保护。 保护位通过专用指令进行设置和清除。 响应于尝试访问从原始数据获得的翻译数据，检查与原始数据相关联的保护位，以确定保护位是否不能指示原始数据的一致性，如果是，则丢弃 启动翻译的数据以便于维持原始数据和翻译数据之间的数据一致性。
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公开(公告)号：US20120331231A1
公开(公告)日：2012-12-27
申请号：US13585268
申请日：2012-08-14
申请人： Michael S. FLOYD , Guy L. GUTHRIE , Karthick RAJAMANI , Gregory A. STILL , Jeffrey A. STUECHELI , Malcolm S. WARE
发明人： Michael S. FLOYD , Guy L. GUTHRIE , Karthick RAJAMANI , Gregory A. STILL , Jeffrey A. STUECHELI , Malcolm S. WARE
IPC分类号： G06F12/08
CPC分类号： G06Q50/10
摘要： An apparatus for providing system memory usage throttling within a data processing system having multiple chiplets is disclosed. The apparatus includes a system memory, a memory access collection module, a memory credit accounting module and a memory throttle counter. The memory access collection module receives a first set of signals from a first cache memory within a chiplet and a second set of signals from a second cache memory within the chiplet. The memory credit accounting module tracks the usage of the system memory on a per user virtual partition basis according to the results of cache accesses extracted from the first and second set of signals from the first and second cache memories within the chiplet. The memory throttle counter for provides a throttle control signal to prevent any access to the system memory when the system memory usage has exceeded a predetermined value.
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