公开(公告)号：US4654830A

公开(公告)日：1987-03-31

申请号：US675379

申请日：1984-11-27

申请人： H. T. Chua ,  Cyrus Tsui ,  Albert Chan ,  Gary Gouldsberry

发明人： H. T. Chua ,  Cyrus Tsui ,  Albert Chan ,  Gary Gouldsberry

IPC分类号： G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  G11C13/00

CPC分类号： G11C29/78

摘要： Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages.The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.

摘要翻译： 提供了用于替换熔丝阵列PROM中的存储器的有缺陷行（或列）的装置，其包括禁用缺陷行并编程冗余行以响应缺陷行的地址。 还提供了用于减小高和低地址电压之间的摆动的装置。 冗余行通过保险丝通过与门连接到地址缓冲区的所有ADDRESS和＆Upbar＆AS /线，以便冗余行始终关闭，直到编程为止。 如果找到有缺陷的行，则有缺陷的行中的所有存储单元被禁用，并且冗余行被编程，通过选择性地吹送导致ADDRESS和＆amp; upbar＆AS /线的熔丝，从而使得冗余行响应缺陷行的地址。

公开(公告)号：US4670708A

公开(公告)日：1987-06-02

申请号：US635861

申请日：1984-07-30

申请人： Bob Bosnyak ,  Albert Chan ,  Mark Fitzpatrick ,  Gary Gouldsberry ,  Cyrus Tsui ,  Andrew K. Chan

发明人： Bob Bosnyak ,  Albert Chan ,  Mark Fitzpatrick ,  Gary Gouldsberry ,  Cyrus Tsui ,  Andrew K. Chan

IPC分类号： G11C29/00 ,  G01R31/02 ,  G11C17/00 ,  G11C29/02 ,  G11C29/04 ,  G11C29/50

CPC分类号： G11C29/50008 ,  G01R31/025 ,  G11C29/02 ,  G11C29/50 ,  G11C17/14

摘要： Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.

摘要翻译： 提供电路用于测试易熔链路周围短路的易熔链路阵列。 每个链路都是电隔离的，并与一对基准可熔链路进行比较，以检测短路的存在与否。

公开(公告)号：US4634898A

公开(公告)日：1987-01-06

申请号：US554474

申请日：1983-11-22

申请人： Gary Gouldsberry ,  Albert Chan ,  Cyrus Tsui ,  Mark Fitzpatrick

发明人： Gary Gouldsberry ,  Albert Chan ,  Cyrus Tsui ,  Mark Fitzpatrick

IPC分类号： H03K19/013 ,  H03K19/088 ,  H03K17/04 ,  H03K17/60

CPC分类号： H03K19/013 ,  H03K19/0136 ,  H03K19/088

摘要： A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.

摘要翻译： 独特的双反相缓冲器具有第一装置，用于反转和隔离数字输入信号，第二装置重新转换并进一步隔离输入信号，以及包括输出晶体管94的输出装置。双反相缓冲器配置有主动上拉电阻， 输出晶体管92的下降装置。通过双重反转缓冲器的高到低的传播延迟时间和低到高的传播延迟时间通过使用有源下拉装置而减少。 输出晶体管的快速关断是通过将晶体管耦合到其基极来实时地将其截止的。 在优选实施例中，钳位电路201用于将输出电压保持在最大预定电平，以进一步减少将输出电压降低到逻辑“0”状态所花费的时间。