公开(公告)号：US20230080101A1

公开(公告)日：2023-03-16

申请号：US17930112

申请日：2022-09-07

申请人： HAESUNG DS CO., LTD.

发明人： Dong Jin YOON ,  Sung Il KANG ,  In Seob BAE ,  Seok Kyu SEO ,  Dong Young PYEON

IPC分类号： H01L23/12 ,  H01L23/00 ,  H01L21/48 ,  H01L23/053

摘要： Provided are a semiconductor package substrate, a method of manufacturing the semiconductor package substrate, and a semiconductor package. According to one embodiment of the present disclosure, a semiconductor package substrate includes a base substrate having a lower surface in which a first trench is provided and an upper surface in which a second trench and a third trench are provided, including a circuit pattern and a conductive material; a first resin arranged in the first trench; and a second resin arranged in the second trench and the third trench, wherein the second trench exposes at least a part of the first resin.

公开(公告)号：US20210098268A1

公开(公告)日：2021-04-01

申请号：US16854704

申请日：2020-04-21

申请人： HAESUNG DS CO., LTD.

发明人： Dong Young PYEON ,  Sung Il KANG ,  Jong Hoe KU ,  In Seob BAE

IPC分类号： H01L21/48

摘要： According to an embodiment of the disclosure, a method of fabricating a carrier for a wafer level package (WLP) by using a lead frame, wherein the lead frame is fabricated by forming a trench and a post by performing first half etching on an upper surface of a base substrate comprising a conductive material, filling the first-half-etched surface with resin of an insulating material, removing the resin exposed to outside of the trench so that an upper surface of the trench and an upper surface of the resin are at a same level, and performing second half etching on a lower surface of the base substrate, in which a memory chip is attached to the lower surface of the base substrate.