公开(公告)号：US20150365099A1

公开(公告)日：2015-12-17

申请号：US14303733

申请日：2014-06-13

Applicant: Hamilton Sundstrand Corporation

Inventor： James Saloio ,  Kanwalpreet Reen

IPC: H03M1/12

CPC classification number: H03M1/122 ,  G01D5/2291

Abstract: A signal convertor includes a first sensor configured to generate a first signal and a second signal and first and second multiplexers configured receive the first and second signals, respectively, and generate samples. The signal convertor also includes an analog-to-digital (A/D) convertor configured to convert the samples and a processor configured to multiply the samples by a sine vector and by a cosine vector and determine a magnitude of the first and second signals based upon the product of the samples and the sine vector and the product of the samples and the cosine vector. A method for converting a signal is also disclosed.

Abstract translation: 信号转换器包括被配置为产生第一信号和第二信号的第一传感器，并且配置的第一和第二多路复用器分别接收第一和第二信号，并产生采样。 信号转换器还包括被配置为转换样本的模数（A / D）转换器和经配置以将样本乘以正弦矢量和余弦矢量的处理器，并且基于第一和第二信号的幅度确定 对样品和正弦载体的乘积和样品和余弦载体的乘积进行比较。 还公开了一种转换信号的方法。

公开(公告)号：US09007087B2

公开(公告)日：2015-04-14

申请号：US13649586

申请日：2012-10-11

Applicant: Hamilton Sundstrand Corporation

Inventor： Steven A. Avritch ,  Kanwalpreet Reen

IPC: G01R31/40 ,  G01R31/02 ,  G01R27/26

CPC classification number: G01R31/028 ,  G01R27/2605

Abstract: A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time. The memory device is connected to store the duration of time measured by the hold-up power storage device following a loss of normal power.

Abstract translation: 利用故障检测电路自动检测滞留电力存储装置的故障。 故障检测电路包括保持监视电路和存储器件。 保持监视电路连接到监视保持功率存储装置的输出，其中保持监视电路测量保持功率存储装置在正常功率损耗之后提供足够功率的持续时间，以及 根据测量的持续时间检测故障。 存储器件被连接以存储在停止正常功率之后由保持功率存储设备测量的持续时间。

公开(公告)号：US11783235B2

公开(公告)日：2023-10-10

申请号：US16715964

申请日：2019-12-16

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen ,  Richard A. Poisson ,  Joshua Robert Dunning

IPC: G06N20/10 ,  G05B17/02 ,  G06N3/045 ,  G06N7/01 ,  G06N3/044

CPC classification number: G06N20/10 ,  G05B17/02 ,  G06N7/01 ,  G05B2219/24182 ,  G06N3/044 ,  G06N3/045

Abstract: A machine learning system that includes one or more machine learning models implemented in one or more hardware processors, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the one or more machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

公开(公告)号：US20230161773A1

公开(公告)日：2023-05-25

申请号：US17455899

申请日：2021-11-19

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen ,  Richard A. Poisson

IPC: G06F16/2455

CPC classification number: G06F16/24568

Abstract: Apparatus and associated methods relate to mitigating data-stream dropout in a serial data-stream. A time-sequence of messages of the serial data-stream is received, each containing a data packet communicating an action. Validity of each of the time-sequence of messages received is determined. After receiving each valid message, a plurality of future actions is created based at least in part on the valid message received. The plurality of future actions corresponds to a plurality of future data packets of the time-sequence of messages. After receiving each valid message, the action communicated in the valid message received is performed. After receiving each invalid messages, a next one of the set of sequential future actions created is instead used in place of any action communicated in the data packet of the invalid message received.

公开(公告)号：US09391630B2

公开(公告)日：2016-07-12

申请号：US14303733

申请日：2014-06-13

Applicant: Hamilton Sundstrand Corporation

Inventor： James Saloio ,  Kanwalpreet Reen

IPC: H03M1/12 ,  G01D5/22

CPC classification number: H03M1/122 ,  G01D5/2291

Abstract: A signal convertor includes a first sensor configured to generate a first signal and a second signal and first and second multiplexers configured receive the first and second signals, respectively, and generate samples. The signal convertor also includes an analog-to-digital (A/D) convertor configured to convert the samples and a processor configured to multiply the samples by a sine vector and by a cosine vector and determine a magnitude of the first and second signals based upon the product of the samples and the sine vector and the product of the samples and the cosine vector. A method for converting a signal is also disclosed.

Abstract translation: 信号转换器包括被配置为产生第一信号和第二信号的第一传感器，并且配置的第一和第二多路复用器分别接收第一和第二信号，并产生采样。 信号转换器还包括被配置为转换样本的模数（A / D）转换器和经配置以将样本乘以正弦矢量和余弦矢量的处理器，并且基于第一和第二信号的幅度确定 对样品和正弦载体的乘积和样品和余弦载体的乘积进行比较。 还公开了一种转换信号的方法。

公开(公告)号：US11914599B2

公开(公告)日：2024-02-27

申请号：US17455899

申请日：2021-11-19

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen ,  Richard A. Poisson

IPC: G06F16/2455

CPC classification number: G06F16/24568

Abstract: Apparatus and associated methods relate to mitigating data-stream dropout in a serial data-stream. A time-sequence of messages of the serial data-stream is received, each containing a data packet communicating an action. Validity of each of the time-sequence of messages received is determined. After receiving each valid message, a plurality of future actions is created based at least in part on the valid message received. The plurality of future actions corresponds to a plurality of future data packets of the time-sequence of messages. After receiving each valid message, the action communicated in the valid message received is performed. After receiving each invalid messages, a next one of the set of sequential future actions created is instead used in place of any action communicated in the data packet of the invalid message received.

公开(公告)号：US20170299409A1

公开(公告)日：2017-10-19

申请号：US15131706

申请日：2016-04-18

Applicant: Hamilton Sundstrand Corporation

Inventor： Gary L. Hess ,  Kanwalpreet Reen

IPC: G01D5/22

Abstract: A resolver system includes a rotatable primary winding, a secondary winding fixed relative to the primary winding, and an analog-to-digital converter electrically connected to the secondary winding. A control module is operatively connected to analog-to-digital converter and is responsive to instructions to apply an excitation voltage with an oscillating waveform to the primary winding, induce a secondary voltage using the secondary winding using the excitation voltage, and acquire a plurality of voltage measurements from the secondary winding separated by a time interval corresponding to π/3 of the excitation voltage oscillating waveform.

公开(公告)号：US20140103955A1

公开(公告)日：2014-04-17

申请号：US13649586

申请日：2012-10-11

Applicant: HAMILTON SUNDSTRAND CORPORATION

Inventor： Steven A. Avritch ,  Kanwalpreet Reen

IPC: G01R31/40

CPC classification number: G01R31/028 ,  G01R27/2605

Abstract: A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time. The memory device is connected to store the duration of time measured by the hold-up power storage device following a loss of normal power

Abstract translation: 利用故障检测电路自动检测滞留电力存储装置的故障。 故障检测电路包括保持监视电路和存储器件。 保持监视电路连接到监视保持功率存储装置的输出，其中保持监视电路测量保持功率存储装置在正常功率损耗之后提供足够功率的持续时间，以及 根据测量的持续时间检测故障。 存储器件被连接以存储在停止正常功率之后由保持功率存储设备测量的持续时间

公开(公告)号：US20210182737A1

公开(公告)日：2021-06-17

申请号：US16715964

申请日：2019-12-16

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen ,  Richard A. Poisson ,  Joshua Robert Dunning

IPC: G06N20/10 ,  G06N7/00 ,  G05B17/02

Abstract: A machine learning system that includes one or more machine learning models implemented in one or more hardware processors, a first-level feature creation module, and a combination module provides an output based on one or more channel inputs. Each of the one or more machine learning models receives the channel inputs and additional feature inputs based on the channel inputs to produce the output. The first-level feature creation module receives the channel inputs, performs a feature creation operation, creates the additional feature inputs, and provides the additional feature inputs to at least one of the machine learning models. The first-level feature creation operation performs a calculation on one or more aspects of the channel inputs, and the combination module receives the one or more machine learning model outputs and produce a machine learning channel output.

公开(公告)号：US10540213B2

公开(公告)日：2020-01-21

申请号：US15914121

申请日：2018-03-07

Applicant: Hamilton Sundstrand Corporation

Inventor： Kirk A. Lillestolen ,  Kanwalpreet Reen

IPC: G06F9/52 ,  G01R31/00

Abstract: A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.