公开(公告)号：US20250105655A1

公开(公告)日：2025-03-27

申请号：US18371807

申请日：2023-09-22

Applicant: Hamilton Sundstrand Corporation

Inventor： Steven A. Avritch ,  Michael A. Wilson ,  Alexander Trotman

IPC: H02J7/34 ,  H01R12/73 ,  H02J7/00

Abstract: A capacitive system includes a module circuit card assembly including a first modular keying and alignment mechanism and a second modular keying and alignment mechanism. The first and second modular keying and alignment mechanisms are configured for mechanical alignment and electrical connection with a backplane circuit card assembly (CCA). A capacitor is mounted to the module circuit card assembly and is electrically connected to each of the first and second modular keying and alignment mechanisms through a charge/discharge circuit. The circuit is configured to: charge the capacitor with the module circuit card assembly connected to the backplane CCA, discharge the capacitor with the module circuit card assembly connected to the backplane CCA for providing backup power, and discharge the capacitor through a bleed resistor of the circuit upon disconnection of the module circuit card assembly from the backplane CCA.

公开(公告)号：US11100025B2

公开(公告)日：2021-08-24

申请号：US16112244

申请日：2018-08-24

Applicant: Hamilton Sundstrand Corporation

Inventor： Christopher Brian Noll ,  Steven A. Avritch

IPC: G06F13/40 ,  B64C13/50 ,  B64C19/00

Abstract: A system includes a computing system and a cable connector. The computing system includes a plurality of processors and an interconnect circuit configured to connect the plurality of processors to each other. The cable connector is configured to connect to the interconnect circuit and provide a channel identifier to the computing system, and the interconnect circuit is configured to set one of the plurality of processors as a system controller based on the channel identifier.

公开(公告)号：US10785073B1

公开(公告)日：2020-09-22

申请号：US16443078

申请日：2019-06-17

Applicant: Hamilton Sundstrand Corporation

Inventor： Christopher Brian Noll ,  Jeffrey A. Eldridge ,  Steven A. Avritch ,  Peter Martin Gilbert

IPC: H03K7/08 ,  H04L25/49 ,  G05B19/05 ,  G06F7/575 ,  G05B19/045

Abstract: A pulse width modulation signaling system includes a first control channel that is configured to receive a hardware Boolean command input from a first hardware status monitor, receive a software multi-bit command input from a first software system, and generate a first pulse width modulated signal that is representative of the Boolean command input and the software multi-bit command input. The hardware Boolean command input is a binary value of either a first state or a second state, the software multi-bit command input includes a binary value of either a first state or a second state, and the first pulse width modulated signal defines a duty cycle.

公开(公告)号：US20190296675A1

公开(公告)日：2019-09-26

申请号：US16441368

申请日：2019-06-14

Applicant: Hamilton Sundstrand Corporation

Inventor： Steven A. Avritch

IPC: H02P25/06 ,  H02K16/04 ,  H02K41/03 ,  H02K41/02 ,  H02K11/21 ,  H02K1/34 ,  H02K1/12 ,  H02K11/38

Abstract: A linear motor actuator includes a plurality of stators mounted stationary relative to one another along a common actuation axis. A translator rod is mounted to the stators for linear motion relative to the stators along the actuation axis, wherein each stator is magnetically coupled to the translator rod to drive motion of the translator rod along the actuation axis.

公开(公告)号：US20190235025A1

公开(公告)日：2019-08-01

申请号：US15881278

申请日：2018-01-26

Applicant: HAMILTON SUNDSTRAND CORPORATION

Inventor： Steven A. Avritch ,  David F. Dickie

IPC: G01R31/34 ,  G01R31/42 ,  G01R31/06 ,  H02P27/06

CPC classification number: G01R31/343 ,  G01R31/06 ,  G01R31/346 ,  G01R31/42 ,  H02P21/22 ,  H02P27/06 ,  H02P29/0241

Abstract: A method of detecting a fault in a sinusoidally controlled permanent magnet synchronous motor (PMSM). The method includes receiving a first rotor reference frame current demand, the first rotor reference frame current demand based on a current control for the PMSM and receiving a first rotor reference frame current feedback, the first rotor reference frame current feedback corresponding to the first rotor reference frame current demand received. The method also includes computing a first error of the rotor reference frame current based on the first rotor reference frame current demand and the first rotor reference frame current feedback and identifying a fault of the sinusoidally controlled PMSM if the first error exceeds a first selected threshold for a first selected duration.

公开(公告)号：US20160274195A1

公开(公告)日：2016-09-22

申请号：US14663250

申请日：2015-03-19

Applicant: HAMILTON SUNDSTRAND CORPORATION

Inventor： MARK J. COLLINS ,  Ronald Daley ,  Steven A. Avritch

IPC: G01R31/40 ,  H02M3/158

CPC classification number: G01R31/40 ,  H02M3/158

Abstract: A power system includes a first power input, a second power input, a power output, a first ideal diode coupled to the a power input and a power output and a second ideal diode coupled to a second power input and the power output. The power system also includes a first switching circuit coupled to the first power input and the first ideal diode and a second switching circuit coupled to the second power input and the second ideal diode, the switching circuits operating as an open or a short circuit based on an input. The power system also includes a test controller coupled to the first switching circuit, the second switching circuit and the power output and configured to determine an operating status of the power system based on an input to the first switch, inputs to the second switch and the power output.

Abstract translation: 电力系统包括第一电力输入，第二电力输入，电力输出，耦合到电力输入的第一理想二极管和功率输出以及耦合到第二电力输入和功率输出的第二理想二极管。 电力系统还包括耦合到第一电力输入端和第一理想二极管的第一开关电路和耦合到第二电力输入端和第二理想二极管的第二开关电路，开关电路作为开路或短路工作，基于 一个输入 电力系统还包括耦合到第一开关电路，第二开关电路和电力输出的测试控制器，并且被配置为基于对第一开关的输入来确定电力系统的运行状态，输入到第二开关和 功率输出。

公开(公告)号：US20140103955A1

公开(公告)日：2014-04-17

申请号：US13649586

申请日：2012-10-11

Applicant: HAMILTON SUNDSTRAND CORPORATION

Inventor： Steven A. Avritch ,  Kanwalpreet Reen

IPC: G01R31/40

CPC classification number: G01R31/028 ,  G01R27/2605

Abstract: A fault detection circuit is utilized to automatically detect faults in hold-up power storage devices. The fault detection circuit includes a hold-up monitoring circuit and a memory device. The hold-up monitoring circuit is connected to monitor output of the hold-up power storage device, wherein the hold-up monitoring circuit measures a duration of time that the hold-up power storage device provides sufficient power following a loss of normal power and detects faults based on the measured duration of time. The memory device is connected to store the duration of time measured by the hold-up power storage device following a loss of normal power

Abstract translation: 利用故障检测电路自动检测滞留电力存储装置的故障。 故障检测电路包括保持监视电路和存储器件。 保持监视电路连接到监视保持功率存储装置的输出，其中保持监视电路测量保持功率存储装置在正常功率损耗之后提供足够功率的持续时间，以及 根据测量的持续时间检测故障。 存储器件被连接以存储在停止正常功率之后由保持功率存储设备测量的持续时间

公开(公告)号：US20240380335A1

公开(公告)日：2024-11-14

申请号：US18315044

申请日：2023-05-10

Applicant: Hamilton Sundstrand Corporation

Inventor： Naison E. Mastrocola ,  Steven A. Avritch

IPC: H02M7/487 ,  H02M7/5387 ,  H02P21/22 ,  H02P25/03 ,  H02P25/16 ,  H02P27/06

Abstract: A motor drive system includes a three-phase motor and a virtual neutral bridge inverter circuit. The three-phase motor includes a first phase lead, a second phase lead, and a third phase lead. Each of the first phase neutral end, the second phase neutral end, and the third phase neutral end of the phase leads are separated from one another. The virtual neutral bridge inverter circuit includes a first neutral switch pair connected at a first neutral connection node, a second neutral switch pair connected at a second neutral connection node, and a third neutral switch pair connected at a third neutral connection node. The first phase neutral end is connected to the first neutral connection node, the second phase neutral end is connected to the second neutral connection node, and the third phase neutral end is connected to the third neutral connection node.

公开(公告)号：US11417486B2

公开(公告)日：2022-08-16

申请号：US16601112

申请日：2019-10-14

Applicant: Hamilton Sundstrand Corporation

Inventor： Richard A. Poisson ,  Steven A. Avritch

IPC: H01H51/10 ,  G01R31/327 ,  H01H50/32 ,  H01H51/12 ,  H01H51/27 ,  H03K3/78 ,  H03K5/131

Abstract: A method of controlling the behavior of a latching relay includes receiving a configuration signal of either a first behavior signal or a second behavior signal, receiving a power status signal of either a powered or unpowered signal, receiving either a low-to-high or a high-to-low signal command signal, generating latching pulse in response to receiving a powered signal input as the power status signal and a low-to-high signal as the command signal, generating an unlatching pulse in response to receiving a powered signal input as the power status signal and a high-to-low signal as the command signal input, and generating an unlatching pulse in response to receiving the second behavior signal as the configuration signal and the unpowered signal as the power status signal.

公开(公告)号：US11300986B2

公开(公告)日：2022-04-12

申请号：US17175583

申请日：2021-02-12

Applicant: Hamilton Sundstrand Corporation

Inventor： Michael A. Wilson ,  Steven A. Avritch ,  Gary L. Hess

IPC: G05F1/46 ,  B64D41/00 ,  H02J1/10 ,  G05F1/595 ,  G05F1/575

Abstract: A system comprises a first current balancer and a second current balancer. Each of the first and second current balancers includes a first input line for a first voltage source connected to a first output, a second input line for a second voltage source connected to a second output and is in parallel with the first input line, a first series pass element connected in series with the first input line, and a second series pass element connected in series with the second input line. The system further includes a controller operatively connected to the first series pass element and to the second series pass element to throttle at least one of the first series pass element and the second series pass element to balance output current in the first and second outputs.