DISPLAY PANEL AND DISPLAY DEVICE
    2.
    发明申请

    公开(公告)号:US20220399378A1

    公开(公告)日:2022-12-15

    申请号:US17606736

    申请日:2020-12-24

    IPC分类号: H01L27/12 G09G3/20

    摘要: A display panel includes a driving circuit and a signal line. The signal line includes at least two main signal sub-lines each including a first end and a second end, the first ends of the at least two main signal sub-lines are electrically coupled to each other, and the second ends thereof are electrically coupled to each other. N main signal sub-lines in the at least two main signal sub-lines are directly electrically coupled to the driving circuit. Each of the N main signal sub-lines is a direct-coupled main signal sub-line, and a main signal sub-line in the at least two main signal sub-lines other than the direct-coupled main signal sub-lines is an indirect-coupled main signal sub-line which is not directly electrically coupled to the driving circuit but electrically coupled to the driving circuit via the direct-coupled main signal sub-line, where N is a positive integer.

    SHIFT REGISTER CIRCUIT, DRIVING METHOD THEREOF, GATE DRIVER AND DISPLAY PANEL

    公开(公告)号:US20190221163A1

    公开(公告)日:2019-07-18

    申请号:US16134472

    申请日:2018-09-18

    IPC分类号: G09G3/3266 G09G3/36 G11C19/28

    摘要: A shift register circuit includes an input terminal, a reset terminal, a first scan voltage terminal, a second scan voltage terminal, a first reference voltage terminal, a second reference voltage terminal, a clock terminal, an output terminal, an input circuit, a first control circuit, a second control circuit, and an output circuit. The first control circuit is configured to supply a second reference voltage applied at the second reference voltage terminal to a first node and bring the second reference voltage terminal into conduction with the output terminal in response to a second node being at an active potential. The second control circuit is configured to supply a first reference voltage applied at the first reference voltage terminal to the first node and bring the first reference voltage terminal into conduction with the output terminal in response to a third node being at an active potential.