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公开(公告)号:US20210272491A1
公开(公告)日:2021-09-02
申请号:US16074369
申请日:2018-01-26
发明人: Ying WANG , Li SUN , Fengjing TANG , Hongmin LI
摘要: A shift register unit, a driving method thereof, a gate drive circuit and a display device are provided. The shift register unit includes: an input circuit, an output circuit, a pull-down control circuit and a pull-down circuit; and the output circuit is connected to a first DC power supply terminal, a second clock signal terminal, a pull-up node, a first driving signal output terminal and a second driving signal output terminal respectively, and is configured to output a first power supply signal of the first DC power supply terminal to the first driving signal output terminal under control of the pull-up node.
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公开(公告)号:US20220399378A1
公开(公告)日:2022-12-15
申请号:US17606736
申请日:2020-12-24
发明人: Wei XUE , Fengjing TANG , Hongmin LI
摘要: A display panel includes a driving circuit and a signal line. The signal line includes at least two main signal sub-lines each including a first end and a second end, the first ends of the at least two main signal sub-lines are electrically coupled to each other, and the second ends thereof are electrically coupled to each other. N main signal sub-lines in the at least two main signal sub-lines are directly electrically coupled to the driving circuit. Each of the N main signal sub-lines is a direct-coupled main signal sub-line, and a main signal sub-line in the at least two main signal sub-lines other than the direct-coupled main signal sub-lines is an indirect-coupled main signal sub-line which is not directly electrically coupled to the driving circuit but electrically coupled to the driving circuit via the direct-coupled main signal sub-line, where N is a positive integer.
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公开(公告)号:US20210350734A1
公开(公告)日:2021-11-11
申请号:US16479484
申请日:2019-01-03
发明人: Ying WANG , Hongmin LI , Dong WANG , Fengjing TANG
摘要: The present disclosure provides a shift register unit, including an input sub-circuitry, a pull-up node control sub-circuitry, a pull-down node control sub-circuitry, a gate driving output sub-circuitry and a carry signal output sub-circuitry. The input sub-circuitry is connected to an input end, a second clock signal input end and a pull-up node. The pull-up node control sub-circuitry is connected to the pull-up node, a pull-down node, a first clock signal input end and a first voltage input end. The pull-down node control sub-circuitry is connected to the pull-down node, the pull-up node, the first clock signal input end, the first voltage input end and a second voltage input end.
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4.
公开(公告)号:US20190251891A1
公开(公告)日:2019-08-15
申请号:US16174634
申请日:2018-10-30
发明人: Fengjing TANG , Zhifu DONG , Jian TAO , Hongmin LI
CPC分类号: G09G3/2092 , G09G2310/0202 , G09G2310/0267 , G09G2310/0286 , G11C19/28
摘要: The disclosure relates to a shift register unit, a driving method of shift register units, a gate driving circuit and a display panel. The shift register unit includes: an input module, a pull-up module, a storage capacitor, an output module configured to transmit a first voltage signal to a signal output terminal under the control of the first voltage signal; and an output control module configured to transmit the first voltage signal or a second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a first selection signal, and to transmit the first voltage signal or the second power signal to the signal output terminal under the control of the voltage signal of the pull-up node and a second selection signal.
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公开(公告)号:US20240302701A1
公开(公告)日:2024-09-12
申请号:US18667966
申请日:2024-05-17
发明人: Liqing LIAO , Hongmin LI , Silin FENG , Ying WANG , Fengjing TANG
IPC分类号: G02F1/1362 , G02F1/1368
CPC分类号: G02F1/136286 , G02F1/1368
摘要: An array substrate and a reflective display substrate are disclosed. The array substrate includes a base, and a plurality of data lines and a plurality of sub-pixels that are disposed on the base. The sub-pixel includes a reflective pixel electrode and a TFT. An orthographic projection of the pixel electrode in each sub-pixel on the base is overlapped with orthographic projections of a first electrode, a first data line and a second data line.
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6.
公开(公告)号:US20190237023A1
公开(公告)日:2019-08-01
申请号:US16205305
申请日:2018-11-30
发明人: Ying WANG , Meng LI , Hongmin LI , Dong WANG , Fengjing TANG
IPC分类号: G09G3/3266 , G09G3/36 , G11C19/28
CPC分类号: G09G3/3266 , G09G3/3677 , G09G2310/0286 , G09G2310/06 , G11C19/28
摘要: A shift register and a method for driving the same, a gate driving circuit and a display device. The shift register includes: an input sub-circuit configured to provide a signal at the signal input terminal to the pull-up node under control of the first clock signal terminal; an output sub-circuit configured to provide a clock signal at the second clock signal terminal to the signal output terminal under control of the pull-up node; and a pull-down sub-circuit configured to provide a signal at the power supply terminal to the signal output terminal under control of the third clock signal terminal.
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公开(公告)号:US20190221163A1
公开(公告)日:2019-07-18
申请号:US16134472
申请日:2018-09-18
发明人: Wei XUE , Hongmin LI , Zhifu DONG , Fengjing TANG
IPC分类号: G09G3/3266 , G09G3/36 , G11C19/28
摘要: A shift register circuit includes an input terminal, a reset terminal, a first scan voltage terminal, a second scan voltage terminal, a first reference voltage terminal, a second reference voltage terminal, a clock terminal, an output terminal, an input circuit, a first control circuit, a second control circuit, and an output circuit. The first control circuit is configured to supply a second reference voltage applied at the second reference voltage terminal to a first node and bring the second reference voltage terminal into conduction with the output terminal in response to a second node being at an active potential. The second control circuit is configured to supply a first reference voltage applied at the first reference voltage terminal to the first node and bring the first reference voltage terminal into conduction with the output terminal in response to a third node being at an active potential.
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