公开(公告)号：US20190065118A1

公开(公告)日：2019-02-28

申请号：US16073534

申请日：2016-03-31

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Naveen MURALIMANOHAR ,  Ali SHAFIEE ARDESTANI ,  Ben FEINBERG

IPC: G06F3/06 ,  G11C13/00

Abstract: In an example, a method includes receiving input data and dividing the input data into a plurality of data portions, wherein the size of each data portion is based on a significance level. The input data may be assigned to at least one resistive memory array. Assigning the input data to at least one resistive memory array may comprises at least one of (i) assigning at least one data portion of the input data to be represented by a resistive memory array representing a number of bits, wherein the number of bits represented within the resistive memory array is based on the size of the at least one data portion; and (ii) processing each data portion of the input data with at least one resistive memory array.

公开(公告)号：US20190034201A1

公开(公告)日：2019-01-31

申请号：US16073650

申请日：2016-01-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Naveen MURALIMANOHAR ,  Ali SHAFIEE ARDESTANI

IPC: G06F9/30 ,  G06F17/16 ,  G06N3/063 ,  H03M3/00

Abstract: Examples disclosed herein include a dot product engine, which includes a resistive memory array to receive an input vector, perform a dot product operation on the input vector and a stored vector stored in the memory array, and output an analog signal representing a result of the dot product operation. The dot product engine includes a stored negation indicator to indicate whether elements of the stored vector have been negated, and a digital circuit to generate a digital dot product result value based on the analog signal and the stored negation indicator.