公开(公告)号：US20180365147A1

公开(公告)日：2018-12-20

申请号：US15748639

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thierry FEVRIER ,  David F HEINRICH ,  William C HALLOWELL ,  Mark S FLETCHER ,  Justin Haanbyull PARK ,  David W ENGLER

IPC: G06F12/0804 ,  G06F11/14

Abstract: A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.

公开(公告)号：US20180364928A1

公开(公告)日：2018-12-20

申请号：US15748645

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Justin Haanbyull PARK ,  Thierry FEVRIER ,  David F HEINRICH ,  David W ENGLER

IPC: G06F3/06 ,  G06F1/30 ,  G06F9/4401 ,  G06F9/50

Abstract: A computing device having firmware, an uninterruptible power supply (UPS), and a memory module with volatile memory. Firmware tasks are prioritized to elevate tasks associated with the copying of the contents of the volatile memory to the nonvolatile memory external to the memory module during the loss of main or primary power.