公开(公告)号：US20170242593A1

公开(公告)日：2017-08-24

申请号：US15500072

申请日：2015-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Dwight D. RILEY ,  Joseph E. FOSTER ,  Thierry FEVRIER

IPC: G06F3/06 ,  G06F13/28

CPC classification number: G06F3/065 ,  G06F3/0617 ,  G06F3/0619 ,  G06F3/067 ,  G06F3/0679 ,  G06F3/0688 ,  G06F11/14 ,  G06F11/2071 ,  G06F13/16 ,  G06F13/28

Abstract: According to an example, data may be replicated using a dual-port nonvolatile dual in-line memory module (NVDIMM). A processor may request, through a first port of the dual-port NVDIMM, to store data to universal memory of the dual-port NVDIMM and to commit the data to remote storage according to a high-availability storage capability of the dual-port NVDIMM. The process may then receive a notification from the dual-port NVDIMM that the data has been transparently committed to the remote storage through a second port of the dual-port NVDIMM.

公开(公告)号：US20180364928A1

公开(公告)日：2018-12-20

申请号：US15748645

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Justin Haanbyull PARK ,  Thierry FEVRIER ,  David F HEINRICH ,  David W ENGLER

IPC: G06F3/06 ,  G06F1/30 ,  G06F9/4401 ,  G06F9/50

Abstract: A computing device having firmware, an uninterruptible power supply (UPS), and a memory module with volatile memory. Firmware tasks are prioritized to elevate tasks associated with the copying of the contents of the volatile memory to the nonvolatile memory external to the memory module during the loss of main or primary power.

公开(公告)号：US20180225201A1

公开(公告)日：2018-08-09

申请号：US15746841

申请日：2015-07-23

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thierry FEVRIER ,  David C VALDEZ ,  Patrick A RAYMOND ,  Justin Haanbyull PARK ,  David P MOHR ,  Hai Ngoc NGUYEN ,  Michael Edward MCGOWEN

IPC: G06F12/0804

CPC classification number: G06F12/0804 ,  G06F11/1441 ,  G06F11/1446 ,  G06F11/2015 ,  G06F12/16 ,  G06F2212/1032

Abstract: A method for preserving volatile memory across a computer system disruption includes identifying a set of volatile memory. The set of volatile memory represents a portion of data in volatile memory to preserve during a system disruption. The method includes receiving a system event. The system event indicates that a computer system disruption will occur and that the set of volatile memory is to be written to a stable storage device. The method includes writing the set of volatile memory to the stable storage device to create a stored data set.

公开(公告)号：US20180365147A1

公开(公告)日：2018-12-20

申请号：US15748639

申请日：2015-07-31

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Thierry FEVRIER ,  David F HEINRICH ,  William C HALLOWELL ,  Mark S FLETCHER ,  Justin Haanbyull PARK ,  David W ENGLER

IPC: G06F12/0804 ,  G06F11/14

Abstract: A system and method for a computing device having a processor, a memory module including volatile memory for random access memory (RAM), and an integrated circuit to intercept an error signal from the processor, the intercept delaying a system shutdown of the computing device. Firmware is executed by the processor to copy contents of the volatile memory to a non-volatile memory during the delay of the system shutdown.

公开(公告)号：US20180267860A1

公开(公告)日：2018-09-20

申请号：US15761096

申请日：2015-09-18

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Joseph E FOSTER ,  Thierry FEVRIER ,  James Alexander FUXA

IPC: G06F11/14 ,  G06F12/06 ,  G06F12/16

CPC classification number: G06F11/1441 ,  G06F11/14 ,  G06F11/1456 ,  G06F12/0246 ,  G06F12/0646 ,  G06F12/16 ,  Y02D10/13

Abstract: A system for achieving memory persistence includes a volatile memory, a non-volatile memory, and a processor. The processor may indicate a volatile memory range for the processor to backup, and open a memory window for the processor to access. The system further includes a power supply. The power supply may provide power for the processor to backup the memory range of the volatile memory. The processor may, responsive to an occurrence of a backup event, initiate a memory transfer using the opened memory window. The memory transfer uses the processor to move the memory range of the volatile memory to a memory region of the non-volatile memory.