公开(公告)号：US20240211212A1

公开(公告)日：2024-06-27

申请号：US18601259

申请日：2024-03-11

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Craig Warner ,  Eun Sub Lee ,  Sai Rahul Chalamalasetti ,  Martin Foltin

IPC: G06F7/544 ,  G06F9/38 ,  G06F9/52 ,  G06F40/20 ,  G06N3/063

CPC classification number: G06F7/5443 ,  G06F9/3867 ,  G06F9/522 ,  G06F40/20 ,  G06N3/063

Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

公开(公告)号：US11947928B2

公开(公告)日：2024-04-02

申请号：US17017557

申请日：2020-09-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Craig Warner ,  Eun Sub Lee ,  Sai Rahul Chalamalasetti ,  Martin Foltin

IPC: G06F7/544 ,  G06F9/38 ,  G06F9/52 ,  G06F40/20 ,  G06N3/063

CPC classification number: G06F7/5443 ,  G06F9/3867 ,  G06F9/522 ,  G06F40/20 ,  G06N3/063

Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

公开(公告)号：US20220075597A1

公开(公告)日：2022-03-10

申请号：US17017557

申请日：2020-09-10

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Craig Warner ,  Eun Sub Lee ,  Sai Rahul Chalamalasetti ,  Martin Foltin

IPC: G06F7/544 ,  G06F9/52 ,  G06F9/38 ,  G06N3/063 ,  G06F40/20

Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

公开(公告)号：US12254395B2

公开(公告)日：2025-03-18

申请号：US17027628

申请日：2020-09-21

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Glaucimar Da Silva Aguiar ,  Francisco Plínio Oliveira Silveira ,  Eun Sub Lee ,  Rodrigo Jose Da Rosa Antunes ,  Joaquim Gomes Da Costa Eulalio De Souza ,  Martin Foltin ,  Jefferson Rodrigo Alves Cavalcante ,  Lucas Leite ,  Arthur Carvalho Walraven Da Cunha ,  Monycky Vasconcelos Frazao ,  Alex Ferreira Ramires Trajano

IPC: G06F15/78 ,  G06F17/16 ,  G06N3/063

Abstract: Systems and methods are provided to improve traditional chip processing. Using crossbar computations, the convolution layer can be flattened into vectors, and the vectors can be grouped into a matrix where each row or column is a flattened filter. Each submatrix of the input corresponding to a position of a convolution window is also flattened into a vector. The convolution is computed as the dot product of each input vector and the filter matrix. Using intra-crossbar computations, the unused space of the crossbars is used to store replicas of the filters matrices and the unused space in XIN is used to store more elements of the input. In inter-crossbar computations, the unused crossbars are used to store replicas of the filters matrices and the unused XINs are used to store more elements of the input. Then, the method performs multiple convolution iterations in a single step.

公开(公告)号：US20210110243A1

公开(公告)日：2021-04-15

申请号：US16598329

申请日：2019-10-10

Applicant: Hewlett Packard Enterprise Development LP

Inventor： CRAIG WARNER ,  Chris Michael Brueggen ,  Eun Sub Lee

IPC: G06N3/063 ,  G06N5/04 ,  G06F9/38 ,  G06F9/52 ,  G06K9/62

Abstract: Systems are methods are provided for implementing a deep learning accelerator system interface (DLASI). The DLASI connects an accelerator having a plurality of inference computation units to a memory of the host computer system during an inference operation. The DLASI allows interoperability between a main memory of a host computer, which uses 64 B cache lines, for example, and inference computation units, such as tiles, which are designed with smaller on-die memory using 16-bit words. The DLASI can include several components that function collectively to provide the interface between the server memory and a plurality of tiles. For example, the DLASI can include: a switch connected to the plurality of tiles; a host interface; a bridge connected to the switch and the host interface; and a deep learning accelerator fabric protocol. The fabric protocol can also implement a pipelining scheme which optimizes throughput of the multiple tiles of the accelerator.