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    Adjustable precision for multi-stage compute processes
    2.
    发明授权
    Adjustable precision for multi-stage compute processes 有权

    公开(公告)号：US11385863B2

    公开(公告)日：2022-07-12

    申请号：US16052218

    申请日：2018-08-01

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Sai Rahul Chalamalasetti ,  Paolo Faraboschi ,  Martin Foltin ,  Catherine Graves ,  Dejan S. Milojicic ,  Sergey Serebryakov ,  John Paul Strachan

    IPC: G06F7/483 ,  G06N3/08 ,  G06N3/063

    Abstract: Disclosed techniques provide for dynamically changing precision of a multi-stage compute process. For example, changing neural network (NN) parameters on a per-layer basis depending on properties of incoming data streams and per-layer performance of an NN among other considerations. NNs include multiple layers that may each be calculated with a different degree of accuracy and therefore, compute resource overhead (e.g., memory, processor resources, etc.). NNs are usually trained with 32-bit or 16-bit floating-point numbers. Once trained, an NN may be deployed in production. One approach to reduce compute overhead is to reduce parameter precision of NNs to 16 or 8 for deployment. The conversion to an acceptable lower precision is usually determined manually before deployment and precision levels are fixed while deployed. Disclosed techniques and implementations address automatic rather than manual determination or precision levels for different stages and dynamically adjusting precision for each stage at run-time.

    ERROR CORRECTION CODE IN MEMORY
    4.
    发明申请
    ERROR CORRECTION CODE IN MEMORY 审中-公开

    公开(公告)号：US20180276068A1

    公开(公告)日：2018-09-27

    申请号：US15468619

    申请日：2017-03-24

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Gregg B. Lesartre ,  Craig Warner ,  Martin Foltin ,  Chris Michael Brueggen ,  Brian S. Birk ,  Harvey Ray

    IPC: G06F11/10 ,  G11C29/52 ,  H03M13/29

    CPC classification number: H03M13/2906 ,  G06F11/1048 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/0411

    Abstract: In one example in accordance with the present disclosure, a system comprises a plurality of memory dies, a first region of memory allocated for primary ECC spread across a first subset of at least one memory die belonging to the plurality of memory die, wherein a portion of the primary ECC is allocated to each data block and a second region of memory allocated for secondary ECC spread across a second subset of at least one memory die included in the plurality of memory die. The system also comprises a memory controller configured to determine that an error within the first data block cannot be corrected using a first portion of the primary ECC allocated to the first data block, access the second region allocated for secondary ECC stored on the at least one memory die belonging to the plurality of memory die and attempt to correct the error using the primary and secondary ECC.

    DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY
    7.
    发明申请
    DETERMINING A CURRENT IN A MEMORY ELEMENT OF A CROSSBAR ARRAY 审中-公开

    公开(公告)号：US20170271001A1

    公开(公告)日：2017-09-21

    申请号：US15500040

    申请日：2015-01-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Naveen Muralimanohar ,  Rajeev Balasubramonian ,  Martin Foltin

    IPC: G11C13/00

    Abstract: A method of determining a current in a memory element of a crossbar array is described. In the method, a number of pre-access operations are initiated. Each pre-access operation includes discarding a previously stored sneak current, determining a new sneak current for the crossbar array, discarding a previously stored sneak current, and storing the new sneak current. In the method, in response to a received access command, an access voltage is applied to a target memory element of the crossbar array and an element current for the target memory element is determined based on an access current and a stored sneak current.

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