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    MACHINE LEARNING MODEL BIAS DETECTION AND MITIGATION
    3.
    发明申请
    MACHINE LEARNING MODEL BIAS DETECTION AND MITIGATION 有权

    公开(公告)号：US20220121885A1

    公开(公告)日：2022-04-21

    申请号：US17074201

    申请日：2020-10-19

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Sai Rahul Chalamalasetti ,  Dejan S. Milojicic ,  Sergey Serebryakov

    IPC: G06K9/62 ,  G06N20/00 ,  G06F17/18

    Abstract: Testing for bias in a machine learning (ML) model in a manner that is independent of the code/weights deployment path is described. If bias is detected, an alert for bias is generated, and optionally, the ML model can be incrementally re-trained to mitigate the detected bias. Re-training the ML model to mitigate the bias may include enforcing a bias cost function to maintain a level of bias in the ML model below a threshold bias level. One or more statistical metrics representing the level of bias present in the ML model may be determined and compared against one or more threshold values. If one or more metrics exceed corresponding threshold value(s), the level of bias in the ML model may be deemed to exceed a threshold level of bias, and re-training of the ML model to mitigate the bias may be initiated.

    Multi-die dot-product engine to provision large scale machine learning inference applications
    4.
    发明授权
    Multi-die dot-product engine to provision large scale machine learning inference applications 有权

    公开(公告)号：US11947928B2

    公开(公告)日：2024-04-02

    申请号：US17017557

    申请日：2020-09-10

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Craig Warner ,  Eun Sub Lee ,  Sai Rahul Chalamalasetti ,  Martin Foltin

    IPC: G06F7/544 ,  G06F9/38 ,  G06F9/52 ,  G06F40/20 ,  G06N3/063

    CPC classification number: G06F7/5443 ,  G06F9/3867 ,  G06F9/522 ,  G06F40/20 ,  G06N3/063

    Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

    MULTI-DIE DOT-PRODUCT ENGINE TO PROVISION LARGE SCALE MACHINE LEARNING INFERENCE APPLICATIONS
    6.
    发明申请
    MULTI-DIE DOT-PRODUCT ENGINE TO PROVISION LARGE SCALE MACHINE LEARNING INFERENCE APPLICATIONS 有权

    公开(公告)号：US20220075597A1

    公开(公告)日：2022-03-10

    申请号：US17017557

    申请日：2020-09-10

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Craig Warner ,  Eun Sub Lee ,  Sai Rahul Chalamalasetti ,  Martin Foltin

    IPC: G06F7/544 ,  G06F9/52 ,  G06F9/38 ,  G06N3/063 ,  G06F40/20

    Abstract: Systems and methods are provided for a multi-die dot-product engine (DPE) to provision large-scale machine learning inference applications. The multi-die DPE leverages a multi-chip architecture. For example, a multi-chip interface can include a plurality of DPE chips, where each DPE chip performs inference computations for performing deep learning operations. A hardware interface between a memory of a host computer and the plurality of DPE chips communicatively connects the plurality of DPE chips to the memory of the host computer system during an inference operation such that the deep learning operations are spanned across the plurality of DPE chips. Due to the multi-die architecture, multiple silicon devices are allowed to be used for inference, thereby enabling power-efficient inference for large-scale machine learning applications and complex deep neural networks. The multi-die DPE can be used to build a multi-device DNN inference system performing specific applications, such as object recognition, with high accuracy.

    Allocating Resources of a Memory Fabric
    7.
    发明申请
    Allocating Resources of a Memory Fabric 审中-公开

    公开(公告)号：US20200065150A1

    公开(公告)日：2020-02-27

    申请号：US16110516

    申请日：2018-08-23

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Zhikui Wang ,  Antonio Lain ,  Sai Rahul Chalamalasetti ,  Anshuman Goswami

    IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54 ,  G06F3/06

    Abstract: A method for allocating resources includes determining that an initial allocation of memory bandwidth for one or more computing jobs fails a performance metric. The memory bandwidth provides access to a global memory pool for multiple legacy processors across a memory fabric. The method also includes determining a new allocation of memory bandwidth for the computing jobs that meets the performance metric. Additionally, the method includes assigning the new allocation of memory bandwidth to the computing jobs. The method further includes executing the computing jobs using the new allocation of memory bandwidth.

    PROACTIVE WAVELENGTH SYNCHRONIZATION
    10.
    发明公开
    PROACTIVE WAVELENGTH SYNCHRONIZATION 审中-公开

    公开(公告)号：US20230170991A1

    公开(公告)日：2023-06-01

    申请号：US17539275

    申请日：2021-12-01

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Hyunmin Jeong ,  Sai Rahul Chalamalasetti ,  Marco Fiorentino ,  Peter Jin Rhim

    IPC: H04B10/079

    CPC classification number: H04B10/07955

    Abstract: Examples described herein relate to a method for synchronizing a wavelength of light in an optical device. In some examples, a heater voltage may be predicted for a heater disposed adjacent to the optical device in a photonic chip. The predicted heater voltage may be applied to the heater to cause a change in the wavelength of the light inside the optical device. In response to applying the heater voltage, an optical power inside the optical device may be measured. Further, a check may be performed to determine whether the measured optical power is a peak optical power. If it is determined that measured optical power is the peak optical power, the application of the predicted heater voltage to the heater may be continued.

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