TIME SYNCHRONIZATION WITH MULTI-CHASSIS LINK AGGREGATION

    公开(公告)号:US20250105997A1

    公开(公告)日:2025-03-27

    申请号:US18510958

    申请日:2023-11-16

    Abstract: In some examples, a system provides multi-chassis link aggregation by the first and second electronic devices that are part of a logical device supporting an MCLAG, where the first electronic device includes a first time clock, and the second electronic device includes a second time clock. The first and second time clocks perform, over a link between the first and second electronic devices of the logical device, a clock source selection process to select one of the first and second time clocks as a clock source and another one of the first and second time clocks as a clock sink as part of a time synchronization process in the system.

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