公开(公告)号：US20250141576A1

公开(公告)日：2025-05-01

申请号：US18533718

申请日：2023-12-08

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Tathagata Nandy ,  Chethan Chavadibagilu Radhakrishnabhat ,  Venkatachalam Swaminathan

IPC: H04J3/06

Abstract: In some examples, a first network device including a first time clock sends, over a first network path, a first timing message of a time synchronization process to synchronize the first time clock and a second time clock that is connected to a second network device. The first network device receives an indication associated with a second timing message of the time synchronization process, where the second timing message is to be sent from the second time clock. Based on receiving the indication, the first network device sends a first join message to a first intermediate network device that is part of the first network path, and a second join message to a second intermediate network device that is part of a second network path different from the first network path. The first network device receives, over the first network path, the second timing message sent by the second time clock, the second timing message communicated over the first network path based on the forwarding information built in the first intermediate network device and the second network device.

公开(公告)号：US20250105997A1

公开(公告)日：2025-03-27

申请号：US18510958

申请日：2023-11-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Venkatachalam Swaminathan ,  Jagmeet Singh Hanspal

IPC: H04L7/00

Abstract: In some examples, a system provides multi-chassis link aggregation by the first and second electronic devices that are part of a logical device supporting an MCLAG, where the first electronic device includes a first time clock, and the second electronic device includes a second time clock. The first and second time clocks perform, over a link between the first and second electronic devices of the logical device, a clock source selection process to select one of the first and second time clocks as a clock source and another one of the first and second time clocks as a clock sink as part of a time synchronization process in the system.

公开(公告)号：US20230327981A1

公开(公告)日：2023-10-12

申请号：US17719138

申请日：2022-04-12

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Venkatachalam Swaminathan ,  Venkatavaradhan Devarajan

IPC: H04L45/24 ,  H04L45/42 ,  H04L45/00 ,  H04L45/12

CPC classification number: H04L45/245 ,  H04L45/42 ,  H04L45/22 ,  H04L45/123

Abstract: A system for facilitating traffic redirection for a multi-chassis link aggregation group (MCLAG) is provided. During operation, the system can participate in an MCLAG using a first interface of a first switch. The MCLAG can also include a second interface of a second switch. Based on predetermined unavailability for the first switch, the system can determine a sequence of applications for a plurality of traffic forwarding configurations. A respective configuration can facilitate loop prevention for traffic forwarded via the MCLAG. The system can then apply the plurality of configurations to the first switch based on the sequence of applications to redirect unicast traffic from the first switch to the second switch. Here, applying a respective configuration can include programming corresponding switch hardware with the configuration. Subsequently, the system can perform a set of operations on the first switch that triggers the predetermined unavailability.

公开(公告)号：US20250096918A1

公开(公告)日：2025-03-20

申请号：US18510974

申请日：2023-11-16

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Madhusudanan Rengarajan ,  Sethumohan Kumaran ,  Venkatachalam Swaminathan ,  Selva Pandi Murugesan

IPC: H04J3/06 ,  H04L45/24

Abstract: In some examples, a first electronic device includes a plurality of interfaces to network links that are part of a link aggregation group. A first time clock selects, from the plurality of interfaces based on priorities associated with the plurality of interfaces, a designated interface to use for a time synchronization process, where the priorities include a first priority assigned to a first interface, a second priority assigned to a second interface, and a third priority assigned to a third interface. The first time clock sends, using the designated interface, a timing message of the time synchronization process to a second electronic device that includes a second time clock to which the first time clock of the first electronic device is to be synchronized according to the time synchronization process.